Datasheet

TPS65200
SLVSA48 –APRIL 2010 www.ti.com
INTERRUPT MASK REGISTER 1 (MASK1)
Address – 0x0Bh
DATA BIT D7 D6 D5 D4 D3 D2 D1 D0
VBUSOV
FIELD NAME TSDM Not used Not used Not used Not used Not used WLEDM
PM
READ/WRITE R/W R/W R/W R/W R/W R/W R/W R/W
RESET VALUE 0 0 0 0 0 0 0 0
FIELD NAME BIT DEFINITION
(1)
TSD fault interrupt mask
TSDM 0 – Interrupt not masked
1 – Interrupt masked
VBUS OVP fault interrupt mask
VBUSOVPM 0 – Interrupt not masked
1 – Interrupt masked
Not used N/A
Not used N/A
Not used N/A
Not used N/A
Not used N/A
WLED fault interrupt mask
WLEDM 0 – Interrupt not masked
1 – Interrupt masked
(1) Setting any of the interrupt mask bits does not disable protection circuits. When set, the respective fault will not be signaled on the INT
pin.
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