Datasheet

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TPS65200

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SLVSA48 –APRIL 2010

TERMINAL

NO. I/O DESCRIPTION

NAME

(DSBGA) (QFN)

Charge current-sense input. Battery current is sensed via the voltage drop across an

CSOUT A2 10 I

external sense resistor. A 0.1-mF ceramic capacitor to PGND is required.

Charger input voltage. Bypass it with a 1-mF ceramic capacitor from VBUS to PGND. It

VBUS E1, E2 1, 2 I/O

also provides power to the load in boost mode.

Output of the linear charger and battery voltage sense. Connect the battery from this

BAT A1 9 O

pin to ground.

VSYS C6 22 I Input supply for WLED driver and current shunt monitor

Connection point between reverse blocking MOSFET and high-side switching

PMID D1, D2, D3 3, 4 O MOSFET. Bypass it with a minimum of 1-mF capacitor from PMID to PGND. No other

circuits are recommended to connect at PMID pin.

SWC C1, C2, C3 5, 6 O Internal switch to inductor connection (charger)

Boot-strapped capacitor for the high-side MOSFET gate driver. Connect a 10-nF

BOOT F1 36 O

ceramic capacitor (voltage rating above 10 V) from BOOST pin to SWC pin.

B1, B2, B3,

PGND 7, 8 Power ground

Charge current-sense input. Battery current is sensed via the voltage drop across an

CSIN A3 11 I

external sense resistor. A 0.1-mF ceramic capacitor to PGND is required.

SCL F3 33 I I

C interface clock

SDA F2 35 I/O I

C interface data

Charge status pin. Pulled low when charge in progress. Open drain for other

STAT B4 15 O conditions. This pin can also be controlled through I

C register. STAT can be used to

drive a LED or communicate with a host processor.

Internal supply for battery charger. Connect a 1-mF ceramic capacitor from this output

VDD A4 14 O

to PGND. External load on VDD is not recommended.

DP E4 31 I USB port D+ input connection

DM F4 32 I USB port D- input connection

LDO output. LDO is regulated to 4.9 V and drives 60-mA of current. Bypass LDO to

LDO D6 24 O GND with at least a 1-mF ceramic capacitor. LDO is enabled when VBUS is above the

VBUS UVLO threshold.

SGND B5 17 Signal ground

DGND A6 18 Digital ground

VZERO B6 19 I This pin sets the zero-current output voltage level of the current shunt monitor.

Output of current shunt monitor. For positive currents (into battery) VSHNT > VZERO.

VSHNT C5 21 O

For negative currents (out of the battery) VSHNT < VZERO.

This is the switching node of the LED driver. Connect the inductor from the supply to

SWL F6 27 I the SWL pin. This pin is also used to sense the output voltage for open LED

protection.

Control pin of the LED boost regulator. It is a multi-functional pin which can be used for

CTRL D5 25 I

enable control and PWM dimming.

Output of the transconductance error amplifier. Connect an external capacitor to this

COMP E6 26 O

pin to compensate the regulator.

FB E5 29 I Feedback pin for current. Connect the sense resistor from FB to GND.

The voltage on this pin defines the battery voltage for transitioning from liner charge

(pre-charge) to fast charge. A 10-µA current source is internally connected to this pin.

VSHRT A5 16 I

Connect a resistor from this pin to ground to setup VSHORT reference. If the pin is left

floating or tied to VDD an internal VSHORT reference of 2.1 V is used.

VIO E3 34 I I/O reference voltage. A VIO level above 0.6 V disables automatic D+/D- detection.

Interrupt pin (open drain). This pin is pulled low to signal to the main processor that a

INT D4 23 O

fault has occurred.

Boost control pin. Boost mode is turned on whenever this pin is active. Polarity is user