Datasheet

I/O connections and WLED string are not shown.
TPS65200
SLVSA48 –APRIL 2010 www.ti.com
DATA TRANSMISSION TIMING (continued)
V
BAT
= 3.6 ±5%, T
A
= 25 ºC, C
L
= 100 pF (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SCL = 100 KHz 300
t
f(SDA)
Fall time of SDA Signal ns
SCL = 400 kHz 300
PCB LAYOUT CONSIDERATIONS
As for all switching power supplies, the layout is an important step in the design, especially at high peak currents
and switching frequencies. If the layout is not carefully done, the DCDC converters might show noise problems
and duty cycle jitter. The input capacitors on VBUS and PMID pins should be placed as close as possible to the
input pins for good input voltage filtering. The inductors should be placed as close as possible to the switch pins
to minimize the noise coupling into other circuits. The output capacitors need to be placed directly from the
inductor (charger buck) or Schottky diode (WLED boost) to GND to minimize the ripple current in these traces.
All ground pins need to be connected directly to the ground plane as should all passive components with ground
connections. Figure 59 and Figure 60 show one example for placement and routing of the critical components on
a four layer PCB. In this example all components are placed on the top layer and all routing is done on the top
layer or bottom layer. Layer 2 is a solid ground plane and layer 3 is not used for layout. Please note that all IC
pin connections are notes as [pin number]. E.g. The VSYS pin is referenced as [C6].
Figure 59. Sample Schematic
40 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): TPS65200