Datasheet

P S S P
t
S(DAT)
t
S(STA)
t
S(STO)
t
HIGH
t
H(DA T)
t
H(STA)
t
LOW
t
r(
t
F
t
H( STA)
t
(BUF)
SCL
SDA
TPS65200
www.ti.com SLVSA48 –APRIL 2010
Figure 58. I
2
C Data Transmission Timing
DATA TRANSMISSION TIMING
V
BAT
= 3.6 ±5%, T
A
= 25 ºC, C
L
= 100 pF (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
100
f
(SCL)
Serial clock frequency KHz
400
SCL = 100 kHz 4.7
Bus free time between stop and start
t
(BUF)
µs
condition
SCL = 400 kHz 1.3
SCL = 100 kHz 50
t
(SP)
Tolerable spike width on bus ns
SCL = 400 kHz
SCL = 100 kHz 4.7
t
LOW
SCL low time µs
SCL = 400 kHz 1.3
SCL = 100 kHz 4
t
HIGH
SCL high time µs
SCL = 400 kHz 0.6
SCL = 100 kHz 250
t
S(DAT)
SDA → SCL setup time ns
SCL = 400 kHz 100
SCL = 100 kHz 4.7
t
S(STA)
Start condition setup time µs
SCL = 400 kHz 0.6
SCL = 100 kHz 4
t
S(STO)
Stop condition setup time µs
SCL = 400 kHz 0.6
SCL = 100 kHz 0 3.45
t
H(DAT)
SDA → SCL hold time µs
SCL = 400 kHz 0 0.9
SCL = 100 kHz 4
t
H(STA)
Start condition hold time µs
SCL = 400 kHz 0.6
SCL = 100 kHz 1000
t
r(SCL)
Rise time of SCL Signal ns
SCL = 400 kHz 300
SCL = 100 kHz 300
t
f(SCL)
Fall time of SCL Signal ns
SCL = 400 kHz 300
SCL = 100 kHz 1000
t
r(SDA)
Rise time of SDA Signal ns
SCL = 400 kHz 300
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