Datasheet
Turn on VDP _SRC,
I
DM _SINK
, DP_SW,
and DM_SW
Delay 40ms
DPDM_EN=0
DP_LOW = 0 &
DM_LOW = 1 &
DM_High = 0 ?
NO
Delay 40ms
Wall Charger
I
LIMIT
= 975mA
Done
DPDM_D = 1
YES
DISABLED
VIO < 0.6V?
VBUS > VUVLO ,VBUS
YES
Turn off V
DP _SRC
,
I
DM _SINK
, DP_SW,
and DM_SW
Turn off V
DP_ SRC
,
I
DM _SINK
, DP_SW,
and DM_SW
NO
V
BUS
<V
UVLO ,VBUS
ILIMIT = 500mA
DPDM_EN = 1
Delay 200ms
Delay 40ms
Delay 80ms
USB port
I
LIMIT
= 500mA
DPDM_D = 0
0.8V
0.8V
0.4V
VDP_SRC
IDM_SINK
SW_DPSRC
DP_Low
DM_High
DM_Low
DM
DP
SW_ DP
SW_DM
D+ / D- Detection Circuit
State Machine
(Detection control)
TPS65200
www.ti.com
SLVSA48 –APRIL 2010
Figure 48. Adaptor Identification Algorithm and Block Diagram
Bad Adaptor Detection/Rejection (CHBADI)
At the beginning of the charge cycle, the IC will perform the bad adaptor detection by applying a current sink to
VBUS. If V
VBUS
is higher than V
IN(MIN)
for 30 ms, the adaptor is good and the charge process will begin. However,
if V
VBUS
drops below V
IN(MIN)
, a bad adaptor is detected. Then, the IC will disable the current sink, issue an
interrupt and set the CHBADI interrupt in the INT2 register. After a delay of TINT (2s), the IC will repeat the
adaptor detection process, as shown in Figure 50.
If the battery voltage is high (> 3.8 V) it is possible that the input voltage drops below the battery voltage during
adaptor rejection test. In this case the reverse protection will kick-in and disable the charger. Also note that the
30-mA current sink is turned on for 30 ms only. If the input capacitance is > 500 µF (not recommended) the
adaptor may be accepted although it is not capable of providing 30-mA of current. In theses cases the VDPPM
loop will limit the charging current to maintain the input voltage.
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