Datasheet

PRODUCTPREVIEW

TPS65186

www.ti.com

SLVSB04 –JULY 2011

POWER DOWN SEQUENCE REGISTER 1 (DWNSEQ1)

Address – 0x0Ch

DATA BIT D7 D6 D5 D4 D3 D2 D1 D0

FIELD NAME DDLY4[1:0] DDLY3[1:0] DDLY2[1:0] DDLY1 DFCTR

READ/WRITE R/W R/W R/W R/W R/W R/W R/W R/W

RESET VALUE 1

FIELD NAME BIT DEFINITION

DLY4 delay time set; defines the delay time from STROBE3 to STROBE4 during power-down.

00 – 6 ms

DDLY4[1:0] 01 – 12 ms

10 – 24 ms

11 – 48 ms

DLY3 delay time set; defines the delay time from STROBE2 to STROBE3 during power-down.

00 – 6 ms

DDLY3[1:0] 01 – 12 ms

10 – 24 ms

11 – 4 8ms

DLY2 delay time set; defines the delay time from STROBE1 to STROBE2 during power-down.

00 – 6 ms

DDLY2[1:0] 01 – 12 ms

10 – 24 ms

11 – 48 ms

DLY2 delay time set; defines the delay time from WAKEUP low to STROBE1 during power-down.

DDLY1 0 – 3 ms

1 – 6 ms

At power-down delay time DLY2[1:0], DLY3[1:0], DLY4[1:0] are multiplied with DFCTR[1:0]

DFCTR 0 – 1x

1 – 16x