Datasheet

PRODUCTPREVIEW
TPS65186
www.ti.com SLVSB04 –JULY 2011
POWER UP SEQUENCE REGISTER 1 (UPSEQ1)
Address – 0x0Ah
DATA BIT D7 D6 D5 D4 D3 D2 D1 D0
FIELD NAME UDLY4[1:0] UDLY3[1:0] UDLY2[1:0] UDLY1[1:0]
READ/WRITE R/W R/W R/W R/W R/W R/W R/W R/W
RESET VALUE 0
E2
1
E2
0
E2
1
E2
0
E2
1
E2
0
E2
1
E2
FIELD NAME BIT DEFINITION
DLY4 delay time set; defines the delay time from STROBE3 to STROBE4 during power-up.
00 – 3 ms
UDLY4[1:0] 01 – 6 ms
10 – 9 ms
11 – 12 ms
DLY3 delay time set; defines the delay time from STROBE2 to STROBE3 during power-up.
00 – 3 ms
UDLY3[1:0] 01 – 6 ms
10 – 9 ms
11 – 12 ms
DLY2 delay time set; defines the delay time from STROBE1 to STROBE2 during power-up.
00 – 3 ms
UDLY2[1:0] 01 – 6 ms
10 – 9 ms
11 – 12 ms
DLY1 delay time set; defines the delay time from VN_PG high to STROBE1 during power-up.
00 – 3 ms
UDLY1[1:0] 01 – 6 ms
10 – 9 ms
11 – 12 ms
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