Datasheet

PRODUCTPREVIEW
SLAVE ADDRESS W A REG ADDRESS A SLAVE ADDRESS R A DATA
REGADDR
AS
DATA
REGADDR +n
A DATA
REGADDR + n+1
Ā P
From master to slave
From slave to master
S
W AP
Start
Write (low) AcknowlegeStop
R Read (high)
S
Ā Not Acknowlege
n bytes + ACK
SLAVE ADDRESS W A REG ADDRESS A DATA
REGADDR
AS
DATA
SUBADDR +n
A DATA
SUBADDR +n+1
Ā P
n bytes + ACK
S
1-7 8 9 1-7 8 9 1-7 8 9
P
ADDRESS R/W ACK DATA ACK DATA
ACK/
nACK
STOPSTART
SDA
SCL
t
f
t
HD;STA
t
LOW
t
r
t
HD;DAT
t
SU;DAT
t
HIGH
t
SU;STA
t
HD;STA
t
SP
t
SU;STO
t
r
t
BUF
t
f
S S
r
SP
SDA
SCL
TPS65186
SLVSB04 –JULY 2011 www.ti.com
reception of the data word sent to the device. A stop condition is recognized as a low to high transition of the
SDA input during the high portion of the SCL signal. All other transitions of the SDA line must occur during the
low portion of the SCL signal. An acknowledge is issued after the reception of valid address, sub-address and
data words. The I
2
C interfaces will auto-sequence through register addresses, so that multiple data words can be
sent for a given I
2
C transmission. Reference Figure 29 and Figure 30 for deail.
TOP: Master writes data to slave.
BOTTOM: Master reads data from slave.
Figure 29. I
2
C Data Protocol
Figure 30. I
2
C Start/Stop/Acknowledge Protocol
Figure 31. I
2
C Data Transmission Timing
24 Copyright © 2011, Texas Instruments Incorporated