Datasheet

PRODUCTPREVIEW
VIN
PWRUP
WAKEUP
VNEG
VEE
VPOS
VDDH
PWR_GOOD
VN
VB
1.8ms
(1)
DDLY 2
DDLY 3
DDLY 4
DDLY 1
300us (max)
STANDBY ACTIVE
SLEEP
ACTIVE
(1) Minimum delay time between WAKEUP rising edge and IC rady to accept I 2C transaction .
UDLY 2
UDLY 3
UDLY 1
UDLY 4
I2C
300us (max)
UDLY 2
UDLY 1
UDLY 4
UDLY3
50ms
TPS65186
SLVSB04 –JULY 2011 www.ti.com
In this example the first power-up sequence is started by pulling the PWRUP pin high (rising edge). Power-down is
initiated by pulling the WAKEUP pin low (device enters SLEEP mode). The 2nd power-up sequence is initiated by
pulling the WAKEUP pin high while the PWRUP pin is also high (power up from SLEEP to ACTIVE).
Figure 24. Power-Up and Power-Down Timing Diagram
SOFTSTART
TPS65186 supports soft-start for all rails, i.e. inrush current is limited during startup of DCDC1, DCDC2, LDO1,
LDO2, CP1 and CP2. If DCDC1 or DCDC2 are unable to reach power-good status within 50 ms, the
corresponding UV flag is set in the interrupt registers, the interrupt pin is pulled low, and the device enters
STANDBY mode. LDO1, LDO2, positive and negative charge pumps also have a 50-ms power-good time-out
limit. If either rail is unable to power up within 50 ms after it has been enabled, the corresponding UV flag is set
and the interrupt pin is pulled low. However, the device will remain in ACTIVE mode in this case.
VPOS/VNEG SUPPLY TRACKING
LDO1 (VPOS) and LDO2 (VNEG) track each other in a way that they are of opposite sign but same magnitude.
The sum of VLDO1 and VLOD2 is guaranteed to be < 50 mV.
18 Copyright © 2011, Texas Instruments Incorporated