Datasheet

PRODUCTPREVIEW
UDLY1
ACTIVE bit
or
WAKEUP high
VN PG VB PG
UDLY2
STROBE 1 STROBE 2
UDLY3
STROBE 3
UDLY4
STROBE 4
PG4
STANDBY bit
or
WAKEUP low
STROBE 2STROBE 1
DDLY1 DDLY2 DDLY3
STROBE 3 STROBE 4
DDLY4
50ms
VB
powers up
1
st
rail
powers up
2
nd
rail
powers up
3
nd
rail
powers up
4
th
rail
powers up
4
th
rail
powers down
3
nd
rail
powers down
2
nd
rail
powers down
1
st
rail
powers down
VB
powers down
VN
powers down
VN
powers up
TPS65186
www.ti.com SLVSB04 –JULY 2011
TOP: Power-up sequence is defined by assigning strobes to individual rails. STROBE1 is the first strobe to occur after
ACTIVE bit is set and STROBE4 is the last event in the sequence. Strobes are assigned to rails in UPSEQ0 register
and delays between STROBES are defined in UPSEQ1 register.
BOTTOM: Power-down sequence is independent of power-up sequence. Strobes and delay times for power down
sequence are set in DWNSEQ0 and DWNSEQ1 register.
Figure 23. Power-Up and Power-Down Sequence
Copyright © 2011, Texas Instruments Incorporated 17