Datasheet

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2 Setup and Test Results
2.1 Connections and Jumpers
2.2 Recommended Test Setup
Setup and Test Results
This section explains the input, output, and jumper connections of the TPS65167EVM-277. It also
describes how to set up test equipment for evaluating the EVM and provides test results.
The DEFAULT jumper settings are required for the EVM to operate within the specifications of Table 1 .
Table 2. Default Jumper Settings
Jumper Default Setting
JP1 – LDO INPUT VLOGIC
JP2 – HVS GND
JP3 – EN REGOUT
JP4 – CTRL REGOUT
J1-VAUX/GND: Output voltage for LDO and ground return connection
J2-VIN/GND: Input power supply and ground connection, Vin range 6 V to 14 V
J3-VLOGIC/GND: Output voltage for 3.3-V buck converter and ground return connection
J4-VGL/GND: Output voltage for negative charge pump and ground return connection
J5-VGH/GND: Output connection for the internal high-voltage switch and ground return connection
J6-POUT/GND: Output voltage of the positive charge pump, internally connected to the high-voltage
switch and ground return
J7-Vs/GND: Output connection for the main boost converter and ground return connection
J8-TEMP/GND: Output of internal temperature sensor voltage is proportional to the chip
temperature and ground return
JP2-HVS: When the HVS pin is connected to VIN, high-voltage stress test is enabled (Vs
goes high, and VGH goes to a fixed 30 V). When the HVS pin is connected to
GND, the high-voltage stress test is disabled.
JP3-EN: When connected to GND, unit is OFF; when connected to REGOUT, unit turns on
with no delay between Vin and Vs. When connected to C30 position, unit turns on
with a delay between Vin and Vs set by C30.
JP4-CTRL: Gate voltage shaping function; connect to REGOUT if not used.
Before turning on the power supply, ensure that jumpers JP2--JP4 are in their default positions.
Connect a power supply rated at 3 A or more to provide 6 V to 14 V to J2. Do not exceed 14 V on J2. In
order to avoid voltage drop through the input power supply line, connect heavy gauge, twisted-pair wire to
J2. The output voltages can be monitored by voltmeters and/or an oscilloscope with standard
high-impedance voltage probes.
The output voltages reach their respective regulation voltages per Table 1 after the appropriate soft-start
times and relative delays. Resistive or electronic loads can be attached to output J1 for Vaux, J3 for
Vlogic, and J7 for Vs. Only resistive loads can be attached to outputs J4 for VGL and J5 for VGH.
Exceeding an output load specified in Table 1 results in the output voltage falling out of regulation.
SLVU220 – August 2007 TPS65167EVM-277 3
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