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3 Board Layout
3.1 Board Layout Recommendations
C2P
VIN
EN
SW
SUP
D1
L1
10 Hm
Vin
5.0V
C9
100pF
R2
39 kW
R1
470 kW
FB
Vs
15V/1.0A
C5
22 mF
C6
22 mF
C7
22 mF
C1
22 mF
C2
22 mF
C3
22 mF
C4
1 mF
COMP
C2N
HVS
CTRL
DRN
POS1
NEG1
OUT1
POS2
NEG2
OUT2
ADLY
GDLY
SS
POS3
BGND
OUT3
AGND
REF
FBN
RHVS
FBP
POUT
C1P
C1N
PGND
PGND
VGH
DRVN
D2
D3
R7
160 kW
R8
39 kW
C20
220 nF
C16
330 nF
VGL
-5V/50mA
C15
330 nF
VGH
27.5V/50mA
R5
300
kW
R6
16 kW
C14
100 pF
C13
1
mF
C12
330nF
R4
220 kW
R3
10kW
C10
2.2nF
C11
330nF
C8
1 mF
C17
22 nF
C18
22 nF
C19
22 nF
R10
1kW
TPS65165
SW
33
2
1
17
16
36
5
6
7
10
9
8
14 15 20 11 3 12 23
22
21
18
35
27
28
40
39
38
37
32
34
4
30
2925
24
Board Layout
This chapter provides board layout recommendations as well as pictures of the EVM board layers.
For complete information regarding PC-board layout, please refer to the TPS65165 Data Sheet, literature
number SLVS723 . An excerpt from that document follows:
1. Place the power components outlined in bold first on the PCB.
2. Rout the traces outlined in bold with wide PCB traces
3. Place a 1- µ F bypass capacitor directly from the Vin pin to GND since this is the supply pin for internal
circuits.
4. Place a 1- µ F bypass capacitor directly from the SUP pin to GND since this is the supply pin for internal
circuits.
5. Use a short and wide trace to connect the SUP pin to the output of the boost converter Vs.
6. Place the 220-nF reference capacitor directly from REF to AGND close to the IC pins.
7. The feedback resistor for the negative charge pump between FBN and REF needs to be >40k Ω .
8. Use short traces for the charge pump drive pin (DRVN) of VGL because the traces carry switching
waveforms.
9. Place the flying capacitors as close as possible to the C1P, C1N and C2P, C2N pin.
10. Solder the Power Pad of the QFN package to GND and use thermal vias to lower the thermal
resistance
Figure 2. Layout Recommendation
SLVU203 – March 2007 TPS65165EVM-233 5
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