Datasheet

TPS65161

TPS65161A, TPS65161B

SLVS617E –APRIL 2006–REVISED MARCH 2013

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Layout Consideration

The PCB layout is an important step in the power supply design. An incorrect layout could cause converter

instability, load regulation problems, noise, and EMI issues. Especially with a switching dc-dc converter at high

load currents, too-thin PCB traces can cause significant voltage spikes. Good grounding becomes important as

well. If possible, a common ground plane to minimize ground shifts between analog (GND) and power ground

(PGND) is recommended. Additionally, the following PCB design layout guidelines are recommended for the

TPS65161:

1. Separate the power supply traces for AVIN and VINB, and use separate bypass capacitors.

2. Use a short and wide trace to connect the OS pin to the output of the boost converter.

3. To minimize noise coupling into the OS pin, use a 470-nF bypass capacitor to GND.

4. Place the rectifier diode of the step down converter as close as possible to the SWB pin.

5. Use short traces for the charge-pump drive pins (DRN, DRP) of V

and V

because these traces carry

switching waveforms.

6. Place a 1-μF bypass capacitor from the SUP pin to GND.

7. Place the flying capacitors as close as possible to the DRP and DRN pin, avoiding a high voltage spike at

these pins.

8. Place the Schottky diodes as close as possible to the IC, respective to the flying capacitors connected to the

DRP and DRN.

9. Route the feedback network of the negative charge pump away from the drive pin traces (DRN) of the

negative charge pump. This avoids parasitic coupling into the feedback network of the negative charge pump

giving good output voltage accuracy and load regulation. To do this, use the FREQ pin and trace to isolate

DRN from FBN.

10. Connect a 220-nF capacitor directly from the REF pin (24) to GND (23) for a stable and noise free reference

voltage.

Product Folder Links: TPS65161 TPS65161A TPS65161B