Datasheet

C
dly
++
4.8 mA 2.3 ms
1.213 V
+ 9.4 nF å Cdly + 10 nF
C
dly
+
4.8 mA td
Vref
+
4.8 mA td
1.213 V
with td + Desired delay time
EN2
EN1
GD
V
(LOGIC)
VGL
DLY1
V
S
V ,
GH
V
S
DLY2
V
IN
V
GH
V
IN
FallTimeDependsonLoad
CurrentandFeedbackResistor
TPS65161
TPS65161A, TPS65161B
www.ti.com SLVS617E –APRIL 2006–REVISED MARCH 2013
Figure 18. Power-On Sequencing Using EN1 and EN2
Setting the Delay Times DLY1, DLY2
Connecting an external capacitor to the DLY1 and DLY2 pins sets the delay time. If no delay time is required,
these pins can be left open. To set the delay time, the external capacitor connected to DLY1 and DLY2 is
charged with a constant current source of typically 4.8 μA. The delay time is terminated when the capacitor
voltage has reached the internal reference voltage of V
ref
= 1.213 V. The external delay capacitor is calculated:
Example for setting a delay time of 2.3 ms:
Gate Drive Pin (GD)
This is an open-drain output that goes low when the boost converter, V
S
, is within regulation. The gate drive pin
GD remains low until the input voltage or enable EN2 is cycled to ground.
Undervoltage Lockout
To avoid incorrect operation of the device at low input voltages, an undervoltage lockout is included which shuts
down the device at voltages lower than 6 V.
Input Capacitor Selection
For good input voltage filtering, low ESR ceramic capacitors are recommended. The TPS65161 has an analog
input, AVIN, and two input pins for the buck converter VINB. A 1-μF input capacitor should be connected directly
from the AVIN to GND. Two 22-μF ceramic capacitors are connected in parallel from the buck converter input
VINB to GND. For better input voltage filtering, the input capacitor values can be increased. See Table 1 and the
Application Information section for input capacitor recommendations.
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