Datasheet

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VGH
Q5
I
ADJ
Q6
Vref
1.213 V
CTRL
UVLO
ADJ
CPI
FBP
Cadj
47 pF
Q7
Control
CTRL, UVOL, FPB = High
Q5 = Q7 = ON, Q6 = OFF
CTRL = Low
Q5 = Q7 = OFF, Q6 = Turns ON
toff
VGH
VCPI
VL
ton
toffIadj x
Cadj
V
Control
Signal
(Pin CTRL)
V
Cadj 
Iadj  toff
V
with ladj  200 A
(4)
TPS65150
SLVS576 – SEPTEMBER 2005
DETAILED DESCRIPTION (continued)
Figure 19. Implementation of the Gate voltage shaping
Figure 20. Timing Diagram of the Gate voltage shaping
The control signal applied to CTRL sets the timing of VGH. When CTRL is high, Q5 is turned on and the positive
charge pump voltage applied on CPI is present on VGH. At the same time, the capacitor connected to ADJ is
charged up by Q7 to VGH, while Q6 is turned off. When CTRL is taken low, Q5 and Q7 turn off, and Q6 is slowly
turned on as the capacitor on ADJ is discharged by the discharge current I
ADJ
, typically 200 µA. The capacitor
value on C
ADJ
determines the fall time of VGH. For a given off time (toff), external capacitor Cadj determines the
desired voltage drop, ∆ V.
When the input voltage falls below the undervoltage threshold (UVLO) or the device enters shutdown latch
triggered by the fault delay timer, then VGH is disconnected from CPI by Q5 and is high impedance.
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