Datasheet

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Power-on Sequencing, DLY1, DLY2
VGL
DLY1
VGH, with CTRL=high
DLY2
VIN
GD
Vs
Fall Time of V
S
, VGL and
VGH Depends on Load
Current and Feedback
Resistor Impedance
Setting the Delay Times DLY1, DLY2
C
dly

5 A  td
V
REF

5 A  td
1.213 V
with td  Desired delay time
(3)
Gate Drive, GD
VGH Switch / Gate Voltage Shaping, CPI – VGH
TPS65150
SLVS576 – SEPTEMBER 2005
DETAILED DESCRIPTION (continued)
As soon as the input voltage is applied, and rises above the undervoltage lockout (UVLO), the device starts with
the main boost converter, Vs, coming up first. Then the negative voltage, VGL, comes up, set by the delay time
DLY1; and then the positive charge pump, VGH, set by the delay time DLY2. Finally, the VCOM buffer starts up.
The delay times, DLY1 and DLY2, are set by the capacitor value connected to these pins. An internal current
source charges the capacitor with a constant current of typically 5 µA until the voltage reaches the internal
comparator trip point of Vref = 1.213 V.
Figure 18. Power on Sequencing With CTRL = High
Connecting an external capacitor to the DLY1 and DLY2 pins sets the delay time. If no delay time is required,
these pins can be left open. To set the delay time, the external capacitor connected to DLY1 and DLY2 is
charged with a constant current source of typically 5 µA . The delay time is terminated when the capacitor
voltage has reached the internal reference voltage of Vref = 1.213 V. The external delay capacitor is calculated:
The gate drive pin can be used to drive an external MOSFET, providing isolation for the main boost converter Vs.
The gate drive is an open drain output capable of sinking typically 500 µA. The gate drive is latched low as soon
as the main boost converter, Vs, reaches its power-good threshold. The gate drive signal goes high impedance
when the input voltage falls below the undervoltage lockout (UVLO) or the device enters shutdown latch triggered
by the fault delay.
The gate voltage shaping circuit is used to reduce crosstalk between the LCD pixels by adjusting the fall time of
the positive gate voltage, VGH. The CTRL pin needs to be connected to Vin if the gate voltage shaping function
is not used. This function is implemented by adjusting the fall time of the gate voltage signal, VGH, generated by
the positive charge pump. The fall time can be adjusted with the external capacitor, Cadj connected to the ADJ
pin. The corresponding timing diagram is shown in Figure 20 .
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