Datasheet

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TPS65150
SLVS576 – SEPTEMBER 2005
ELECTRICAL CHARACTERISTICS (continued)
VIN = 3.3 V, Vs = 10 V, T
A
= –40 ° C to 85 ° C, typical values are at T
A
= 25 ° C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
FB
Feedback regulation voltage CTRL = GND, VGH = open 1.187 1.214 1.238 V
I
FB
Feedback input bias current CTRL = GND, VGH = open 10 100 nA
R
DS(on)
Q3 P-Channel switch RDSon I
OUT
= 20 mA 1.1 Ω
I
DRP
= 50 mA, 420 650
V
FBP
= V
FBPNominal
– 5%
V
DropN
Current sink voltage drop
(1)
mV
I
DRP
= 100 mA, 900 1400
V
FBP
= V
FBPNominal
– 5%
Load regulation VGH=24V, Iload=0mA to 20mA 0.07 %/mA
VGH ISOLATION SWITCH, GATE VOLTAGE FALL TIME CONTROL
R
DS(on)
Q5 - Pass MOSFET R
DSon
I
OUT
= 20 mA 12 30 Ω
Iadj Capacitor charge current Vadj = 20 V, CPI = 30 V 160 200 240 µA
Minimum output voltage Vadj = 0 V, I
VGH
= 10 mA 2 V
I
VGH
Maximum output current 20 mA
TIMING CIRCUITS DLY1, DLY2, FDLY
I
DLY1
Drive current into delay capacitor DLY1 V
DLY1
= 1.213 V 3 5 7 µA
I
DLY2
Drive current into delay capacitor DLY1 V
DLY2
= 1.213 V 3 5 7 µA
R
FDLY
Fault time delay resistror
(2)
250 450 650 k Ω
GATE DRIVE (GD)
V
(GD, Vs)
Gate drive threshold
(3)
Vs rising –12% of –4% of V
Vs Vs
V
OL
Gate drive output low voltage I
(sink)
= 500 µA 0.5 V
I
LKG
Gate drive output leakage current V
GD
= 15 V 0.001 1 µA
Vcom Buffer
V
CM
Common mode input range 2.25 (Vs) –2V V
V
os
Input offset voltage I
OUT
= 0 mA –25 25 mV
Io = ± 25 mA –37 37
Io = ± 50 mA –77 55
DC load regulation mV
Io = ± 100 mA –85 85
Io = ± 150 mA –110 110
I
B
VCOMIN Input bias current –300 –30 300 nA
I
peak
Peak output current Vs = 15 V 1.2
Vs = 10 V 0.65 A
Vs = 5 V 0.15
(2) The fault time is calculated as: t
F
= C × R = C × 450 k Ω
(3) The GD signal is latched low when the main boost converter output Vs is within regulation. The GD signal is reset when the input
voltage or enable of the boost converter is cycled low.
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