Datasheet

1516
L1
L1
1
2
VIN
OUTN
3
4
OUTN
VAUX
13
14
L2
L2
6
5
8
12
11
10
9
GND
FBG
FB
EN
PGND
OUTP
OUTP
PGND
Exposed
Thermal Die
RTE Package
(Top View)
7
P0081-01
TPS65135
SLVS704A –NOVEMBER 2011–REVISED NOVEMBER 2011 www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
(1)
T
A
ORDERING P/N PACKAGE PACKAGE MARKING
–40°C to 85°C TPS65135RTE RTE CCR
(1) The RTE package is available in tape and reel. Add R suffix (TPS65135RTER) to order quantities of 3000 parts per reel. For the most
current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at
www.ti.com.
16-PIN TQFN PACKAGE
PIN FUNCTIONS
PIN
I/O DESCRIPTION
NAME NO.
Input pin to enable the device. Pulling this pin high enables the device. This pin has an
EN 8 I
internal 500 kΩ pulldown resistor.
FB 7 I Feedback regulation input for the positive output voltage rail
FBG 6 I Feedback regulation input for GND reference (regulation of the negative output voltage rail)
GND 5 – Analog ground
L1 15, 16 I/O Inductor terminal
L2 13, 14 I/O Inductor terminal
OUTN 2, 3 O Negative output
OUTP 9, 10 O Positive output
PGND 11, 12 – Power GND
VAUX 4 I/O Reference voltage output. This pin requires a 100-nF capacitor for stability.
VIN 1 I Input supply
Exposed thermal die – Connect this pad to analog GND.
2 Copyright © 2011, Texas Instruments Incorporated
Product Folder Links: TPS65135