TPS65120EVMĆ076/ TPS65124EVMĆ076 User’s Guide August 2004 PMP Portable Power SLVU112
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
EVM IMPORTANT NOTICE Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation kit being sold by TI is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not considered by TI to be fit for commercial use.
EVM WARNINGS AND RESTRICTIONS It is important to operate this EVM within the input voltage range described in the EVM User’s Guide. Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are questions concerning the input range, please contact a TI field representative prior to connecting the input power. Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the EVM.
Related Documentation From Texas Instruments Preface About This Manual This user’s guide describes the characteristics, operation, and use of the TPS65120EVM−076 and TPS65124EVM−076 evaluation modules (EVM). Included are EVM specifications, test results, schematic diagram, bill of materials (BOM), and recommended test setup.
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Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Performance Specification Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Modifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents 2−1 2−2 2−3 3−1 3−2 3−3 4−1 Main Output Efficiency vs Load Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Main Output Ripple Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGH and VGL Output Ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Top Assembly Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 1 This chapter contains introductory information about the TPS65120EVM−076 and TPS65124EVM−076 evaluation modules. Topic Page 1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 Performance Specifiction Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.3 Modifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Background 1.1 Background The TPS65120EVM uses a TPS65120 single inductor, multichannel output IC to provide the three output voltages necessary to power amorphous silicon (a−Si) and low-temperature polysilicon (LTPS) TFT-LCD displays. The TPS65120 has integrated power−up/down sequencing and an auxiliary linear regulator providing an additional 3.3-V rail.
Modifications - More Current From VMAIN – An external linear regulator U3 (e.g., TPS79201) powered from BOOT and supporting passives, C14, C15, R17, and R19 can be added to provide more output current for VMAIN. The linear regulator data sheet provides guidance on sizing the supporting passives. Size feedback resistors R17 and R19 so that the regulator output is about 1% below VMAIN. See theTPS6521x data sheet (SLVS531) for guidance on sizing the output capacitor on BOOT relative to C14.
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Chapter 2 This chapter describes how to properly test the TPS65120 and TPS65124 using the TPS65120EVM and TPS65124EVM. Topic Page 2.1 Input/Output Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2 Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.3 Test Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input/Output Connections 2.1 Input/Output Connections The EVM’s input and output connections are described in the following paragraphs. - J1-VIN − This header connects to the positive terminal of the input power supply. - J2-GND − This header connects to the negative terminal of the input pow- er supply. - J3-VGH − This header is the output terminal for the boosted gate voltage, VGH. - J4-GND − This header is a GND terminal. - J7-GND − This header is a GND terminal.
Test Setup 2.2 Test Setup Although the absolute maximum voltage for VIN is 6 V, the TPS6512x family is designed to operate with input voltages of 5.5 V or less. For best results with the EVM as packaged, connect a power supply with a 3.3-V output voltage and current limit set to at least 500 mA. To enable the TPS65120EVM, first short pins 1−2 of jumper JP2 (tie RUN to ON); then short pins 1−2 of jumper JP1 (tie EN to ON).
Test Results Figure 2−2. Main Output Ripple Voltage VBOOT (50 mV/div), AC Coupled VMAIN (10 mV/div), AC Coupled VIN = 3.6 V, VMAIN = 5 V @ 20 mA, VGH = 12 V @ 200 mA, VGL = −12 V @ 200 mA t − Time − 20 ms/div Figure 2−3. VGH and VGL Output Ripple VGH (50 mV/div), AC Coupled VIN = 3.
Chapter 3 The chapter describes the HPA076 PCB board layout and illustrations. Topic 3.1 Page Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Board Layout 3.1 Board Layout Board layout is critical for all switch mode power supplies. Figure 3−1, Figure 3−2, and Figure 3−3 show the board layout for the HPA076 PCB. The switching nodes with high-frequency noise are isolated from the noisesensitive feedback circuitry and special attention has been given to the routing of high-frequency current loops as well as ground. Figure 3−1.
Board Layout Figure 3−2. Top Layer Routing Figure 3−3.
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Chapter 4 ! This chapter provides the TPS65120EVM and TPS65124EVM bill of materials and schematic. Topic Page 4.1 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2 Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bill of Materials 4.1 Bill of Materials Table 4−1. HPA076 Bill of Materials Count RefDes Description Size MFR Part Number −001 −002 1 1 C1 Capacitor, ceramic, 2.2−µF, 6.3−V, X5R, 10% 603 TDK C1608X5R0J225KT 1 1 C10 Capacitor, ceramic, 0.47−µF, 16−V, X5R, 10% 603 TDK C1608X5R1C474KT 1 1 C16 Capacitor, ceramic, 0.1−µF, 25−V, X7R, 10% 603 TDK C1608X7R1E104KT 1 0 C12 Capacitor, ceramic, 0.22−µF, 16−V, X5R, 10% 603 AVX 0603YD224KAT2A 2 2 C2, C13 Capacitor, ceramic, 0.
Schematic Count −001 RefDes −002 U1 1 1 Description Size MFR Part Number IC, Single Inductor Quadruple−Output TFT LCD Power Supply QFN16 TI TPS65120QFN IC, Single Inductor Quadruple−Output TFT LCD Power Supply QFN16 TI TPS65124QFN 0 0 U2 IC, 100 mA Negative Output LDO Linear Regulators SOT23−5 TI TPS72301DBV 0 0 U3 IC, High PSRR, Low Noise LDO, Adj Output, 100−mA SOT23−6 TI TPS79201DBV 1 1 −− PCB, 2.5 In x 2.2 In x .
Schematic Figure 4−1.
