Datasheet
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PIN ASSIGNMENTS
1
2
3
4
12
11
10
9
5 6 7 8
131516
EN
RUN
ENVGL
ENVGH
FBL
FBM
AGND
VMAIN
PGND
BOOT
VGH
FBH
GATE
VIN
SWN
SWP
1
2
3
4
12
11
10
9
5 6
7
8
13141516
EN
RUN
AGND
AGND
FBL
FBM
AGND
VMAIN
PGND
BOOT
VGH
FBH
GATE
VIN
SWP
1
2
3
4
12
11
10
9
5 6
7
8
13141516
Exposed
Thermal Die*
EN
RUN
LDOIN
LDOOUT
FBL
FBM
AGND
VMAIN
PGND
BOOT
VGH
FBH
GATE
VIN
SWN
SWP
AGND
SWN
Exposed
Thermal Die*
AGND
14
Exposed
Thermal Die*
AGND
TPS65120/1/2
(TOP VIEW)
TPS65123
(TOP VIEW)
TPS65124
(TOP VIEW)
TPS65120, TPS65121, TPS65123, TPS65124
SLVS531A – JUNE 2004 – REVISED MARCH 2005
TERMINAL FUNCTIONS
TERMINAL
I/O DESCRIPTION
NAME NO.
VIN 15 I This is the input voltage pin of the device.
This pin can either be the gate driver output to an external small P-Channel MOSFET (see application
GATE 16 I/O section), or an active high control input. Pulling GATE above the 1.4 V logic-high level and RUN to a logic-low
level disables the integrated active power-down sequencing.
RUN controls the external P-Channel MOSFET. This pin must be terminated and not be left floating. Forcing
RUN 2 I
this pin to a logic-high level turns on the external MOSFET switch.
This is the enable pin of the multiple-output dc-to-dc converter. This pin must be terminated and not be left
EN 1 I floating. A simultaneous logic-high level on EN and RUN enables the converter and a logic-low shuts down
the device.
SWN 14 I/O Connect the inductor to this pin. This pin is connected to the source of the high-side MOSFET switch.
SWP 13 I/O Connect the inductor to this pin. This pin is connected to the drain of the low-side MOSFET switch.
PGND 12 O Power ground. Connect to AGND underneath the IC.
VGH 10 O Positive output
Provides a bootstrapped supply for the rectifier MOSFET driver, enabling the gate of the MOSFET to be
BOOT 11 O
driven above the output voltage.
VMAIN 8 I Main output
FBH 9 I Feedback pin for the positive output voltage divider. Regulates to 1.213 V nominal.
Feedback pin for the negative output voltage divider. Regulates to 0 V nominal. Connect feedback resistor
FBL 5 I
divider between VGL and main output.
FBM 6 I Feedback pin for the main output voltage divider. Regulates to 1.213V nominal.
Analog ground. Connect to power ground (PGND) underneath IC. Pins 3 and 4 are only used for AGND in
AGND 7, 3, 4
TPS65123.
Auxiliary linear regulator input. If this pin is connected to GND, the voltage regulator is disabled
LDOIN 3 I (TPS65120/1/2). The low-dropout series-pass regulator (LDO) is enabled according to the GATE signal
timing.
LDOOUT 4 O Auxiliary linear regulator output (TPS65120/1/2).
ENVGL 3 I Enable pin for negative output (TPS65124). This pin should be terminated and not be left floating.
ENVGH 4 I Enable pin for positive output (TPS65124). This pin should be terminated and not be left floating.
6