Datasheet

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SWN
TPS65124
D1
L1
C1
2.2
V
IN
V
GL
C3
220 nF
R4
R3
SWP
FBL
VMAIN
FBM
C5
R6
R5
C4
4.7
BOOT
VGH
C2
220 nF
V
GH
FBH
RUN
GATE
VIN
EN
PGND
AGND
A
A
ENVGH
ENVGL
R2
R1
N&P MOS = VISHAY Si1016
D1 = VISHAY BAT54A−HT3
GPIO1
GPIO2
GPIO3
V
MAIN
N&P MOS
GPIO4
C7
C6
Fµ
Fµ
10 pF
2.2
Fµ
C8
100 nF
10 pF
SWN
TPS65124
D1
L1
C1
V
IN
V
NEG
C3
220 nF
R4
R3
SWP
FBL
VMAIN
FBM
C5
220 nF
R6
R5
C4
1
BOOT
VGH
C2
220 nF
V
POS
FBH
RUN
GATE
VIN
EN
PGND
AGND
A
A
ENVGH
ENVGL
EN
V
POS
R2
R1
R1 = 887 kΩ
R2 = 100 kΩ
R3 = R4 = 680 kΩ
R5 = 845 kΩ
R6 = 270 kΩ
V
REF
µ
F
12 V
−12 V
ENVGH,
ENVGL
(2V/div)
V
GL
(5V/div)
V
GH
(5V/div)
V
IN
= 3.6V
EN = RUN = HIGH
R
GH
= 60 kΩ
R
GL
= 60 kΩ
V
GL
V
GH
SWN
TPS65123 D1
L1
C1
V
IN
V
GL
C3
R4
R3
SWP
FBL
VMAIN
FBM
C5
1uF
R6
R5
V
MAIN
C4
2.2
BOOT
VGH
C2
V
GH
PGND
AGND
FBH
RUN
EN
VIN
A
A
GATE
R2
R1
RUN
LDO
External LDO = TPS792xx series
Ext. LDO nominal output voltage setting recommended at 1% lower than VMAIN.
EN
IN
OUT
µ
F
EN TPS65120
TPS65120, TPS65121, TPS65123, TPS65124
SLVS531A – JUNE 2004 – REVISED MARCH 2005
Figure 26. Fully Programmable Sequencing Featuring Very Low Gate Ripple Voltage
Figure 27. Dual Output Tracking Regulator with High Accuracy Reference Voltage
Figure 28. Boosting Main Output Current, I
MAIN
> 25mA
21