Datasheet
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APPLICATION EXAMPLES
SWN
TPS65120
D1
L1
10
C1
2.2
V
IN
2.7 V to 5.5 V
V
GL
down to −18 V/2 mA
C3
220 nFR4
R3
SWP
FBL
VMAIN
FBM
C5
220 nFR6
R5
V
MAIN
3.0 V to 5.3 V/25 mA
C4
1
BOOT
VGH
C2
220 nF
V
GH
up to +20 V/2 mA
PGND
AGND
FBH
RUN
V
LOGIC
= 3.3 V
EN
VIN
A
A
GATE
LDOIN
LDOOUT
C6
220 nF
R2
R1
GPIO
µF
H
µ
µ
F
SWN
TPS65123
D1
L1
C1
V
IN
2.7 V to 5.5 V
V
GL
C3
220 nF
R4b
R3
SWP
FBL
VMAIN
FBM
C5
220 nF
R6
R5
V
MAIN
C4
1
BOOT
VGH
C2
220 nF
V
GH
PGND
AGND
FBH
RUN
EN
VIN
A
A
GATE
R2
R1
RUN
R4a
N−MOS
VISHAY SI1032
RUN
V
MAIN
= 5.0 V, V
GH
= 15 V, V
GL
= −10 V
R
3
= 540 kΩ, R
4a
= 270 kΩ, R
4b
= 680 kΩ
a4
ldOFFThresho_GL
MAIN
3b4
R
2.1V
V2.1
RR −
−
−
=
a4
3
MAINGL
R
R
VV ×=
µF
SWN
TPS65121
D1
L1
C1
V
IN V
GL1
C3
R4
R3
SWP
FBL
VMAIN
FBM
C5
220 nFR6
R5
V
MAIN
C4
1
BOOT
VGH
C2
220 nF
V
GH
PGND
AGND
FBH
RUN
V
LOGIC
EN
VIN
A A
GATE
LDOIN
LDOOUT
C6
220 nF
R2
R1
GPIO
V
GL2
C7
Negative LDO = TPS723xx series
Negative
LDO
EN
Fµ
C7
>
TPS65120, TPS65121, TPS65123, TPS65124
SLVS531A – JUNE 2004 – REVISED MARCH 2005
Figure 23. Complete TFT-LCD Power Supply from 1 cell Li-Ion
Figure 24. V
GL
→ V
MAIN
Power Down-Sequencing Threshold Shifting
Figure 25. Additonal Negative Gate Driver Voltage
20