Datasheet

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Enable and Power Sequencing (TPS65120/1/2/3)
SWN
TPS65120
D1
L1C1
C3
R4
R3
SWP
FBL
VMAIN
FBM
C5
R6
R5
C4
BOOT
VGH
C2
FBH
RUN
EN
VIN
GATE
R10
R9
C7
P1
PGND
AGND
A A
LDOIN
LDOOUT
V
IN
= 3.3 V
V
GH
V
LOGIC
= 3.3 V
V
GL
V
MAIN
R1
R2
V
IN
RUN
V
LOGIC
, EN
V
MAIN
V
GL
V
GH
V
BOOT
5.75V
GATE, EN_LDOAUX
TPS65120, TPS65121, TPS65123, TPS65124
SLVS531A – JUNE 2004 – REVISED MARCH 2005
DETAILED DESCRIPTION (continued)
To correctly power up most TFT panels, the gate-drive supplies must be sequenced such that the negative
supply (V
GL
) powers up before the positive supply (V
GH
). The TPS65120/1/2/3 controls this sequence through an
enable pin.
Once RUN is high, the TPS65120/1/2/3 turns on the external P-channel MOSFET P1 (see Figure 18 ) by pulling
GATE low. GATE is pulled down with a 100 k Ω resistor. The DC/DC converter then starts, enabling the BOOT
output.
Pulling the enable pin (EN) high enables the MAIN output. When the output voltage V
MAIN
has reached 90% of its
nominal value, the negative output enables. V
GH
is delayed until the negative voltage has reached 90% of its
nominal value.
Pulling the RUN pin low shuts down the device. Power-down sequencing starts by switching off V
GH
and V
GL
.
The V
GH
output capacitor is actively discharged by an internal resistor while V
GL
is only discharged by its
feedback voltage divider. The required time to discharge the output capacitor at V
GL
output depends on the load
current. Once V
FBL
has reached 1.2 V (typ) the main output is turned off followed by the output voltage V
LOGIC
.
This sequence is shown in Figure 19 .
When no power sequencing is required on the digital supply voltage (V
LOGIC
), tie EN and RUN signals together
and GATE can be connected to a logic-high level to disable the power-down sequencer. Each output turns off
depending upon load current and output capacitance.
Figure 18. Power Sequencing on Digital Supply Voltage, Figure 19. TPS65120/1/2/3 Power Sequence
V
LOGIC
15