Datasheet

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DETAILED DESCRIPTION
OPERATION
Soft Start
Undervoltage Lockout
TPS65120, TPS65121, TPS65123, TPS65124
SLVS531A – JUNE 2004 – REVISED MARCH 2005
The standard application circuit ( Figure 1 ) of the TPS65120 is a complete power supply for TFT LCD displays.
The circuit generates four independent supplies for the source driver (V
MAIN
), the gate drivers (V
GH
, V
GL
) and a
logic supply for the timing controller. The input voltage range is from 2.5 V to 5.5 V.
The TPS65120/1/2 contains a high-performance switching regulator and two low-dropout linear regulators
(LDOs). One of the LDOs generates V
MAIN
and the other powers the logic inside the panel. The TPS65123
includes only one linear regulator to provide the main output with low ripple voltage and can be set from 3.0 V to
5.3 V with an external resistor voltage divider. The TPS65124 integrates programmable power sequencing for
highest flexibility.
The TPS6512x generates both positive and negative supply voltages using a single inductor. It alternates
between acting as a step-up converter and an inverting converter on a cycle-by-cycle basis. All output voltages
are independently regulated.
A free-running, variable-peak-current PWM control scheme is used to time-multiplex the inductor between BOOT,
V
GH
, and V
GL
outputs. This inherently-stable control architecture operates at a pseudo fixed frequency, providing
fast response to line and load transients while maintaining a relatively constant switching frequency and high
efficiency over a wide range of input and output voltages.
During the first cycle of operation, internal switches N-MOS1 and P-MOS1 are turned on. SWN connects to VIN,
SWP pulls to ground and the inductor current rises. Once the inductor current reaches the DC current limit (I
LIM
)
of 150 mA (typ) the internal control logic can either turn off N-MOS1 or P-MOS1 to service the requesting output.
Depending on the required output power, the converter starts another cycle or enters a pulse-skipping
modulation scheme to increase efficiency under light loads. The current into the SWN pin measures the inductor
current. The TPS6512x controls the inductor current to regulate BOOT, V
GH
, and V
GL
output voltages.
To achieve low ripple voltage and high accuracy, the main output (V
MAIN
) is post-regulated by an integrated LDO.
This LDO regulator regulates energy from the BOOT output down to 5.3 V (max). To achieve the highest
efficiency, the BOOT voltage is regulated to minimize the dropout voltage across the LDO to approximately V
MAIN
+ 0.5 V.
In addition, the VMAIN, VGH, VGL outputs are monitored for fault conditions that last longer than the fault-timer
period of 100 µs (typ). The device goes into a latched shutdown state in case of a fault condition.
The TPS6512x has an internal soft-start circuit that limits the inrush current during startup. This prevents possible
voltage drops of the input voltage in case the battery or a high impedance power source is connected to the input
of the device.
The device powers up by precharging the BOOT output capacitor to VIN. During the precharge phase, the
current through the rectifying switch N-MOS2 is limited. This also limits the output current under short-circuit
conditions on the BOOT output. To ensure proper startup of the device, the BOOT output must be left unloaded
during the precharge phase.
After the precharge phase, the converter operates with an I
START-UP
current limit of 65 mA (typ), then increases
gradually to the full current limit of 150 mA (typ).
To ensure that the input voltage is high enough for reliable operation, the TPS6512x includes an under-voltage
lockout (UVLO) circuit. The UVLO threshold at the VIN pin is 2.15 V (typ) falling and 2.25 V (typ) rising. The 100
mV (typ) hysteresis prevents supply transients from causing restarts.
Once the input voltage exceeds the UVLO rising threshold, the controller can enable the reference voltage and
precharges BOOT. When the input voltage falls below the UVLO falling threshold, the controller turns off the
reference and all the regulator outputs, and pulls GATE high with an internal 100 k Ω resistor to turn off P1 (
Figure 18 ).
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