Datasheet
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
FB1
FB4
BASE
VIN
SW
SW
PGND
PGND
SUP
VCOM
VCOMIN
FB3
EN
ENR
COMP
FB2
REF
GND
DRV
C1-
C1+
C2-/MODE
C2+
OUT3
Thermal Pad
PWP PACKAGE
(TOP VIEW)
TPS65100-Q1
SLVS849A –JULY 2008–REVISED APRIL 2012
www.ti.com
Terminal Functions
TERMINAL
I/O DESCRIPTION
NAME NO.
VIN 4 I Input voltage pin of the device
Enable pin of the device. This pin should be terminated and not be left floating. A logic high enables the
EN 24 I
device and a logic low shuts down the device.
COMP 22 Compensation pin for the main boost converter. A small capacitor is connected to this pin.
Positive input terminal of the VCOM buffer. When the VCOM buffer is not used, this terminal can be
VCOMIN 11 I
connected to GND to reduce the overall quiescent current of the IC.
Enable pin of the linear regulator controller. This pin should be terminated and not be left floating. Logic
ENR 23 I
high enables the regulator and a logic low puts the regulator in shutdown.
C1+ 16 Positive terminal of the charge pump flying capacitor
C1– 17 Negative terminal of the charge pump flying capacitor
DRV 18 O External charge pump driver
FB2 21 I Feedback pin of negative charge pump
REF 20 O Internal reference output typically 1.23 V
Feedback pin of the linear regulator controller. The linear regulator controller is set to a fixed output
FB4 2 I
voltage of 3.3 V or 3 V depending on the version.
BASE 3 O Base drive output for the external transistor
GND 19 Ground
PGND 7, 8 Power ground
VCOM 10 O VCOM buffer output
FB3 12 I Feedback pin of positive charge pump
OUT3 13 O Positive charge pump output
Negative terminal of the charge pump flying capacitor and charge pump MODE pin. If the flying
capacitor is connected to this pin, the converter operates in a voltage tripler mode. If the charge pump
C2–/MODE 15
needs to operate in a voltage doubler mode, the flying capacitor is removed and the C2–/MODE pin
should be connected to GND.
Positive terminal for the charge pump flying capacitor. If the device runs in voltage doubler mode, this
C2+ 14
pin should be left open.
Supply of the positive and negative charge pump, boost converter gate-drive circuit, and VCOM buffer.
SUP 9 I Should be connected to the output of the main boost converter and cannot be connected to any other
voltage source. For performance reasons, do not connect a bypass capacitor directly to this pin.
FB1 1 I Feedback pin of the boost converter
SW 5, 6 I Switch pin of the boost converter
Thermal pad The exposed thermal pad should be connected to the power ground (PGND).
6 Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS65100-Q1