Datasheet
VIN
COMP
R
C
15 kΩ
C
C
1 nF
f
z
+
1
2 p Cc Rc
TPS65100-Q1
SLVS849A –JULY 2008–REVISED APRIL 2012
www.ti.com
Compensation
The regulator loop can be compensated by adjusting the external components connected to the COMP pin. The
COMP pin is connected to the output of the internal transconductance error amplifier. A typical compensation
scheme is shown in Figure 17.
Figure 17. Compensation Network
The compensation capacitor C
C
adjusts the low frequency gain and the resistor value adjusts the high frequency
gain. The formula below calculates at what frequency the resistor increases the high frequency gain.
Lower input voltages require a higher gain and therefore a lower compensation capacitor value. A good start is
C
C
= 1 nF for a 3.3-V input and C
C
= 2.2 nF for a 5-V input. If the device operates over the entire input voltage
range from 2.7 V to 5.8 V, a large compensation capacitor up to 10 nF is recommended. Figure 18 shows the
load transient with a larger compensation capacitor, and Figure 19 shows a smaller compensation capacitor.
Figure 18. C
c
= 4.7 nF
Figure 19. C
c
= 1 nF
Finally, R
c
needs to be selected. A good practice is to use a 50-kΩ potentiometer and adjust the potentiometer
for best load transient where no oscillations should occur. These tests have to be done at the highest V
in
and
highest load current because converter stability is most critical under these conditions. Figure 20, Figure 21, and
Figure 22 show the fine tuning of the loop with R
c
.
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