Datasheet
TPS65070, TPS65072, TPS65073
TPS650731, TPS650732, TPS650701, TPS650702, TPS650721
www.ti.com
SLVS950G –JULY 2009–REVISED MAY 2013
wLED BOOST CONVERTER
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
L4
voltage at L4 pin 2.8 39 V
Vsink1,2 Input voltage at ISINK1, ISINK2 pins 16 V
V
OUT
Internal overvoltage protection 35 37 39 V
Maximum boost factor (Vout/Vin) Isink1 = Isink2 = 20 mA, Vin = 2.8 V 9 10
T
min_off
Minimum off pulse width 70 ns
R
DS(ON)
N-channel MOSFET on-resistance V
L4
= 3.6 V 0.6 Ω
N-channel MOSFET current limit 0.8 1.6 2.0 A
I
LN_NFET
N-channel leakage current V
DS
= 25 V, T
A
= 25°C 1 μA
Switching frequency 1.125 MHz
V
sink1
, Minimum voltage drop at Isink pin to GND for
400 mV
V
sink2
proper regulation
V
ISET
ISET pin voltage 1.24 V
Iset current = 15 μA 1000
K
ISET
Current multiple Iout/Iset
Iset current = 25 μA 1000
Minimum current into ISINK1, ISINK2 pins For proper dimming (string can be disabled also) 4 mA
I
sink1
, I
sink2
Maximum current into ISINK1, ISINK2 pins Vin = 3.3 V 25 mA
DC current set accuracy Isinkx = 5 mA to 25 mA; no PWM dimming ±5%
Rset1 = 50k; Isink1 = 25 mA, Vin = 3.6 V; no PWM
Current difference between Isink1 and isink2 ±5%
dimming
Rset2 = 250k; Isink1 = 5 mA, Vin = 3.6 V; no PWM
Current difference between Isink1 and Isink2 ±5%
dimming
PWM dimming Bit = 00 –15% 100 15%
PWM dimming Bit = 01 (default) –15% 200 15%
f
PWM
PWM dimming frequency
PWM dimming Bit = 10 –15% 500 15% Hz
PWM dimming Bit = 11 –15% 1000 15%
Rise / fall time of PWM signal For all PWM frequencies 2 μs
Dimming PWM DAC resolution 1%
Reset, PB_IN, PB_OUT, PGood, Power_on, INT, EN_EXTLDO, EN_wLED
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
–15% 20 15%
Input voltage at threshold pin rising; time
100
Reset delay time and PGOOD delay time defined with <PGOOD DELAY0>, <PGOOD ms
200
DELAY1>
400
PB-IN debounce time –15% 50 15% ms
PB_IN “Reset-detect- time” Internal timer –15% 15 15% s
PGOOD low time when PB_IN = Low for >15s –15% 0.5 15% ms
V
IH
High level input voltage on pin POWER_ON 1.2 V
IN
V
V
IH
High level input voltage on pin PB_IN 1.8 AVDD6 V
V
IL
Low Level Input Voltage, PB_IN, Power_on 0 0.4 V
Internal pull-up resistor from PB_IN to AVDD6 50 kΩ
Output current at AVDD6 1 mA
I
IN
Input bias current at Power_on 0.01 1.0 μA
Reset, PB_OUT, PGood, INT output low voltage,
V
OL
I
OL
= 1 mA, Vthreshold < 1 V 0.3 V
EN_EXTLDO
VOH EN_EXTLDO HIGH level output voltage I
OH
= 0.1 mA; optional push pull output VSYS V
I
OL
Reset, PB_OUT, PGood, INT sink current 1 mA
Reset, PB_OUT, PGood, INT open drain
Reset, PB_OUT, PGood,INT output leakage current 0.25 μA
output in high impedance state
V
th
Threshold voltage at THRESHOLD pin Input voltage falling –4% 1 4% V
V
th_hyst
Hysteresis on THRESHOLD pin Input voltage rising 7 mV
I
in
Input bias current at EN_wLED, THRESHOLD 1 μA
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