Datasheet
EN_DCDC3
(drivenfrom
VDCDC1)
EN_EXTLDO
(VDD_RTCIO)
PB_OUT
VLDO1
(VDDPLL)
VDCDC3
(VDD_PDN)
PGOOD
(X_RESET_B)
VDCDC2
(VCC_1V8)
20ms
PB_IN
POWER_ON
canbereleasedHIGHanytime
afterPOWR_ON=HIGH
170 sm
250 sm
assertedHIGHbytheapplicationprocessor
anytimewhile/PB_IN=LOWtokeepthe
systemalive
50msdebounce
SYS
50msdebounce
1ms
VLDO2
(VDD_PRE)
1ms
VDCDC1
(VCC_3V3)
0.95xVout,nominal
170 sm
250 sm
0.95xVout,nominal
BitMASK_EN_DCDC3is
setperdefault.DCDC3is
starttedatthesametime
withLDO2
Bit
MASK_EN_DCDC3
Bit
DS_RDY
Bit
PWR_DS
setBitsPWR_DStoset Titan2
toDEEP SLEEP mode
PWR_DSis
clearedby
PB_INgoing
LOW
DS_RDY=1,startwake-upsequence;
otherwisestartinitialpower-upfromOFFstate
DS_RDY=0,startwith
initialpower-upsequence
0.95xVout,nominal
20ms
setBitsDS_RDY toindicate
memorywasbacked-up
startupfromOFFstate
wakeup
from
DEEP
SLEEP
DS_RDY is
clearedbyuser
software
levelnotdefinedas
voltageatpull-uphas
notrampedatthattime
TPS65070, TPS65072, TPS65073
TPS650731, TPS650732, TPS650701, TPS650702, TPS650721
www.ti.com
SLVS950G –JULY 2009–REVISED MAY 2013
Figure 54. Timing for Sirf Prima DEEP SLEEP Mode
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