Datasheet

EN_DCDC3
(X_PWR_EN)
EN_EXTLDO
(VDD_RTCIO)
PB_OUT
VLDO1
(VDDPLL)
VDCDC3
(VDD_PDN)
PGOOD
(X_RESET_B)
VDCDC2
(VCC_1V8)
20ms
170 sm
PB_IN
250 sm
POWER_ON
canbereleasedHIGHanytime
afterPOWR_ON=HIGH
170 sm
250 sm
assertedHIGHbytheapplicationprocessor
anytimewhile/PB_IN=LOWtokeepthe
systemalive
170 sm 250 sm
50msdebounce
15s
0.5ms
SYS
50msdebounce
1ms
VLDO2
(VDD_PRE)
1ms
VDCDC1
(VCC_3V3)
0.95xVout,nominal
170 sm
250 sm
0.95xVout,nominal
BitMASK_EN_DCDC3is
setperdefault.DCDC3is
starttedwithLDO2
BitMASK_EN_DCDC3isclearedbytheapplicationprocessor.
DCDC3andLDO1areenabled/disabledbyEN_DCDC3to
enter/exitSLEEP mode
Bit
MASK_EN_DCDC3
170 sm
levelnotdefinedas
voltageatpull-uphas
notrampedatthattime
TPS65070, TPS65072, TPS65073
TPS650731, TPS650732, TPS650701, TPS650702, TPS650721
SLVS950G JULY 2009REVISED MAY 2013
www.ti.com
Figure 53. Timing for Sirf Prima SLEEP Mode
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