Datasheet

TPS65070, TPS65072, TPS65073
TPS650731, TPS650732, TPS650701, TPS650702, TPS650721
www.ti.com SLVS950G –JULY 2009–REVISED MAY 2013
Table 9. Sequencing Settings (continued)
DEDICATED DCDC_SQ[2..0] LDO_SQ[2..0] COMMENT
FOR
TPS650701 110 100 DCDC1 = 1.2V automatically enabled (1st)
DCDC2 = 1.8V or 3.3V automatically enabled (2nd)
DCDC3 = 1.8V or 3.3V automatically enabled (3rd)
LDO1 = 1.8V (off per default)
LDO2 = 2.5V, enabled at the same time than DCDC3
PGOOD delay time (reset delay): 400ms <PGOODMASK>=1Dh:
reset based on VDCDC1,2,3 and LDO2
TPS650702 110 001 DCDC1 = 1.2V automatically enabled (1st)
DCDC2 = 1.8V or 3.3V automatically enabled (2nd)
DCDC3 = 1.8V or 3.3V automatically enabled (3rd)
LDO1 = 3.3V (off per default)
LDO2 = 3.3V, automatically enabled after DCDC3 is PGOOD
PGOOD delay time (reset delay): 400ms <PGOODMASK>=1Dh:
reset based on VDCDC1,2,3 and LDO2
TPS65072 Sirf Atlas 4 111 010 DCDC1=VDDIO (3.3V)
DCDC2=VMEM (1.8V)
DCDC3= VDD_PDN (1.2V) driven by X_PWR_EN
LDO1=VDD_PLL (1.2V)
LDO2=VDD_PRE (1.2V)
EN_EXTLDO=VDDIO_RTC
PGOOD delay time (reset delay): 20ms
<PGOODMASK>=10h: reset based on VDCDC1
TPS650721 - 101 100 DCDC1= 2.8V enabled by EN_DCDC1
DCDC2= 2.1V enabled by EN_DCDC2
DCDC3= 2.8V enabled by EN_DCDC3
LDO1= 2.8V (off per default)
LDO2= 2.8V
PGOOD delay time (reset delay): 20ms
<PGOODMASK>=05h: reset based on VDCDC3 and LDO2
TPS65073 OMAP3503 101 001 Supporting SYS-OFF mode:
OMAP3515 Supporting DCDC1=VDDS_WKUP_BG, VDDS_MEM, VDDS,
OMAP3525 SYS-OFF mode VDDS_SRAM (1.8V)
OMAP3530 DCDC2=VDDCORE (1.2V)
DCDC3=VDD_MPU_IVA (1.2V)
LDO1= VDDS_DPLL_DLL, VDDS_DPLL_PER (1.8V)
LDO2=VDDS_MMC1 (1.8V)
PGOOD delay time (reset delay): 400ms
<PGOODMASK>=1Ch: based on VDCDC1, VDCDC2, VDCDC3
TPS650731 OMAP35xx 110 011 DCDC1=VDDS_WKUP_BG, VDDS_MEM, VDDS,
VDDS_SRAM (1.8V)
DCDC2=VDDCORE (1.2V)
DCDC3=VDD_MPU_IVA (1.2V)
LDO1=VDDS_DPLL_DLL (1.8V)
LDO2=VDDA_DAC (1.8V): OFF, enabled by I2C
PGOOD delay time (reset delay): 400ms
<PGOODMASK>=1Ch: reset based on VDCDC1, VDCDC2,
VDCDC3
TPS650732 AM3505 110 001 DCDC1=VDDS1-5 (1.8V)
AM3517 DCDC2=VDDSHV (3.3V)
DCDC3=VDD_CORE (1.2V)
LDO1=VDDA1P8V (1.8V)
LDO2=VDDS_DPLL (1.8V)
PGOOD delay time (reset delay): 400ms
<PGOODMASK>=1Ch: reset based on VDCDC1, VDCDC2,
VDCDC3
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TPS650721