Datasheet
5- 0 5 10 15 20 25 30 35 40 45 50
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
VTS(T)
Temperature-(T)
TPS65070, TPS65072, TPS65073
TPS650731, TPS650732, TPS650701, TPS650702, TPS650721
SLVS950G –JULY 2009–REVISED MAY 2013
www.ti.com
Figure 48. Resulting TS Voltage
As Figure 47 shows, the result is an extended charging temperature range at lower temperatures. The upper
temperature limit is shifted to lower values as well resulting in a V(HOT) temperature of slightly less than 45°C.
Therefore RT3 is needed to shift the temperature range to higher temperatures again. Figure 48 shows the result
for:
• RT2 = 47k
• RT3 = 820R
Using these values will extend the temperature range for charging to –5°C to 50°C.
POWER SOLUTIONS FOR DIFFERENT APPLICATION PROCESSORS
Default Settings
For proper power supply design with TPS6507x, not only the default output voltage is relevant but also in what
sequence the different power rails are enabled. The voltages are typically enabled internally based on the
sequencing options programmed. For different application processors, there are different sequencing options
available. In addition, the delay time and pulse for the reset signal to the application processor is different. See
Table 9 with the default settings for sequencing, output voltages and reset options for the TPS6507x family:
Table 9. Sequencing Settings
DEDICATED DCDC_SQ[2..0] LDO_SQ[2..0] COMMENT
FOR
TPS65070 OMAP-L138 011 001 DCDC1= I/O, (3.3V); enabled by EN_DCDC1
DCDC2= DVDD3318 (1.8V or 3.3V)
(DEFDCDC2=LOW: 1.8V; DEFDCDC2=HIGH: 3.3V)
DCDC3=core voltage CVDD
(DEFDCDC3=LOW: 1.0V; DEFDCDC3=HIGH: 1.2V)
LDO1= 1.8V, delayed by external PMOS
LDO2= 1.2V
PGOOD delay time (reset delay): 400ms <PGOODMASK>=08h:
reset based on VDCDC2
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TPS650721