Datasheet

TPS65070, TPS65072, TPS65073
TPS650731, TPS650732, TPS650701, TPS650702, TPS650721
www.ti.com SLVS950G –JULY 2009–REVISED MAY 2013
DCDC3 CONVERTER
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
VINDCDC
Input voltage range Connected to SYS pin 2.8 6.3 V
3
I
O
Maximum output current TPS65072, TPS650721 Vin > 2.8 V 600 mA
I
O
Maximum output current TPS650701, TPS650702 Vin > 2.8 V 800 mA
TPS65070, TPS65073, TPS650731,
I
O
Maximum output current Vin > 2.8 V 1500 mA
TPS650732
VINDCDC3 = 2.8 V 150 300
R
DS(ON)
High side MOSFET on-resistance mΩ
VINDCDC3 = 3.5 V 120 200
I
LH
High side MOSFET leakage current VINDCDC3 = 6.3 V 2 μA
VINDCDC3 = 2.8 V 200 300
R
DS(ON)
Low side MOSFET on-resistance mΩ
VINDCDC3 = 3.5 V 160 180
I
LL
Low side MOSFET leakage current V
DS
= 6.3 V 1 μA
I
LIMF
Forward current limit TPS65072/721 2.8 V < V
INDCDC3
< 6.3 V 0.8 1.1 1.5 A
I
LIMF
Forward current limit TPS650701, TPS650702 2.8 V < V
INDCDC3
< 6.3 V 1.1 1.6 2.2 A
I
LIMF
Forward current limit TPS65070/73/731/732 2.8 V < V
INDCDC3
< 6.3 V 2.1 2.4 3.5 A
f
S
Oscillator frequency 1.95 2.25 2.55 MHz
V
out
Adjustable output voltage range External resistor divider 0.6 Vin V
V
ref
Reference voltage 600 mV
Internal resistor divider, I
2
C
V
out
Fixed output voltage range 0.725 3.3 V
selectable (Default setting)
For DEFDCDC3 = LOW 1.0
V
out
Default output voltage for TPS65070
For DEFDCDC3 = HIGH 1.2
V
out
For DEFDCDC3 = LOW 1.8
Default output voltage for TPS650701, TPS650702
For DEFDCDC3 = HIGH 3.3
V
out
For DEFDCDC3 = LOW 1.2
Default output voltage for TPS65072
For DEFDCDC3 = HIGH 1.4
V
V
out
For DEFDCDC3 = LOW 2.8
Default output voltage for TPS650721
For DEFDCDC3 = HIGH 2.8
V
out
For DEFDCDC3 = LOW 1.2
Default output voltage for TPS65073, TPS650731, TPS650732
For DEFDCDC3 = HIGH 1.35
DC output voltage accuracy; PFM mode
(1)
–2% 3%
VINDCDC3 = 2.8 V to 6.3 V;
V
out
0 mA ≤ I
O
≤ 1.5 A
DC output voltage accuracy; PWM mode
(1)
–1.5% 1.5%
Vout DC output voltage accuracy with resistor divider at DEFDCDC3; PFM –2% 3%
VINDCDC3 = VDCDC3 +0.3 V (min
2.8 V) to 6.3 V; 0 mA ≤ I
O
≤ 1.5A
Vout DC output voltage accuracy with resistor divider at DEFDCDC3; PWM –1% 1%
ΔV
OUT
Power save mode ripple voltage I
OUT
= 1 mA, PFM mode
(2)
40 mV
pp
Time from active EN to Start
t
Start
Start-up time 170 μs
switching
Time to ramp from 5% to 95% of
t
Ramp
V
OUT
ramp up time 250 μs
V
OUT
Vo -
power good threshold rising voltage
5%
Vo -
power good threshold falling voltage
10%
R
DIS
Internal discharge resistor at L3 –35% 250 35% Ω
(1) Output voltage specification does not include tolerance of external voltage programming resistors. Output voltage in PFM mode is
scaled to +1% of nominal value.
(2) Configuration L= 2.2 μH, C
OUT
= 10 μF
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Product Folder Links: TPS65070 TPS65072 TPS65073 TPS650731 TPS650732 TPS650701 TPS650702
TPS650721