Datasheet

Vout
1
1
Vin
Vout = Vout + ESR
L 8 Cout
-
æ ö
D ´ ´
ç ÷
´ ¦ ´ ´ ¦
è ø
RMSCout
Vout
1
1
Vin
I = Vout
L
2 3
-
´ ´
´ ¦
´
TPS65070, TPS65072, TPS65073
TPS650731, TPS650732, TPS650701, TPS650702, TPS650721
SLVS950G –JULY 2009–REVISED MAY 2013 www.ti.com
(6)
At nominal load current the inductive converters operate in PWM mode and the overall output voltage ripple is
the sum of the voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging and
discharging the output capacitor:
(7)
Where the highest output voltage ripple occurs at the highest input voltage Vin.
At light load currents the converters operate in Power Save Mode and the output voltage ripple is dependent on
the output capacitor value. The output voltage ripple is set by the internal comparator delay and the external
capacitor. The typical output voltage ripple is less than 1% of the nominal output voltage.
Input Capacitor Selection/Input Voltage
Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is
required for best input voltage filtering and minimizing the interference with other circuits caused by high input
voltage spikes. The converters need a ceramic input capacitor of 10μF. The input capacitor can be increased
without any limit for better input voltage filtering.
The input voltage for the step-down converters needs to be connected to pin VINDCDC1/2 for DCDC1 and
DCDC2 and to pin VINDCDC3 for DCDC3. These pins need to be tied together to the power source on pin SYS
(output of the power path). The 3 step-down converters must not be supplied from different input voltages.
Table 5. Possible Capacitors
22 μF 0805 TDK C2012X5R0J226MT Ceramic
22 μF 0805 Taiyo Yuden JMK212BJ226MG Ceramic
10 μF 0805 Taiyo Yuden JMK212BJ106M Ceramic
10 μF 0805 TDK C2012X5R0J106M Ceramic
Output Voltage Selection
The DEFDCDC2 and DEFDCDC3 pins are used to set the output voltage for step-down converter DCDC2 and
DCDC3. See table 1 for the default voltages if the pins are pulled to GND or to Vcc.
Voltage Change on DCDC2 and DCDC3
The output voltage of DCDC2 and DCDC3 can be changed during operation from e.g. 1.0V to 1.2V (TPS65070)
and back by toggling the DEFDCDC2 or DEFDCDC3 pin. The status of the DEFDCDC3 pin is sensed during
operation and the voltage is changed as soon as the logic level on this pin changes from low to high or vice
versa.
The output voltage for DCDC2 and DCDC3 can also be changed by changing the register content in registers
DEFDCDC2_LOW, DEFDCDC2_HIGH, DEFDCDC3_LOW and DEFDCDC3_HIGH.
LDOs
OUTPUT CAPACITOR SELECTION
The control loop of the LDOs is compensated such that it reqires a minimum of 2.2uF as an output capacitor.
Ceramic X5R or X7R capacitors should be used.
INPUT CAPACITOR SELECTION
The input voltage for the two LDOs should be bybassed by a ceramic capacitor of 2.2uF minimum.
66 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: TPS65070 TPS65072 TPS65073 TPS650731 TPS650732 TPS650701 TPS650702
TPS650721