Datasheet
TPS65070, TPS65072, TPS65073
TPS650731, TPS650732, TPS650701, TPS650702, TPS650721
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SLVS950G –JULY 2009–REVISED MAY 2013
The DEFSLEW register defines the slew rate of the output voltage for DCDC2 and DCDC3 in case the voltage is
changed during operation. In case Bit “LDO2 tracking“ in register DEFLDO2 is set, this is also valid for LDO2.
When the voltage change is initiated by toggling pin DEFDCDC2 or DEFDCDC3, the start of the voltage change
is triggered by the rising or falling edge of the DEFDCDC2 or DEFDCDC3 pin. If a voltage change is done
internally be re-programming register DEFDCDC2_LOW, DEFDCDC2_HIGH, DEFDCDC3_LOW or
DEFDCDC3_HIGH, the voltage change is initiated immediately after the new value has been written to the
register with the slew rate defined.
SLEW2 SLEW SLEW VDCDC3
1 0 SLEW RATE
0 0 0 0.11 mV/μs
0 0 1 0.22 mV/μs
0 1 0 0.45 mV/μs
0 1 1 0.9 mV/μs
1 0 0 1.8 mV/μs
1 0 1 3.6 mV/μs
1 1 0 7.2 mV/μs
1 1 1 Immediate
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