Datasheet

t
r
CLK
DATA
STA STO
t(
BUF)
STO
t
h(STA)
t
h(DATA)
t
su(DATA)
t
su(STA)
t
h(STA)
t
su(STO)
t
(LOW)
t
(HIGH)
t
f
STA
TPS65070, TPS65072, TPS65073
TPS650731, TPS650732, TPS650701, TPS650702, TPS650721
SLVS950G –JULY 2009–REVISED MAY 2013 www.ti.com
Figure 44. Serial I/f Timing Diagram
MIN MAX UNIT
f
MAX
Clock frequency 400 kHz
t
wH(HIGH)
Clock high time 600 ns
t
wL(LOW)
Clock low time 1300 ns
t
R
SDAT and CLK rise time 300 ns
t
F
SDAT and CLK fall time 300 ns
t
h(STA)
Hold time (repeated) START condition (after this period the first clock pulse is generated) 600 ns
t
su(STA)
Setup time for repeated START condition 600 ns
t
h(SDAT)
Data input hold time 0 ns
t
su(SDAT)
Data input setup time 100 ns
t
su(STO)
STOP condition setup time 600 ns
t
(BUF)
Bus free time 1300 ns
Note: rise and fall time t
R
and t
F
for the SDAT and CLK signals are defined for 10% to 90% of V(INT-LDO) which
is 2.2V
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