Datasheet

STARTCondition

DATA

CLK

STOP Condition

S P

Dataline

stable;

datavalid

DATA

CLK

Change

ofdata

allowed

TPS65070, TPS65072, TPS65073

TPS650731, TPS650732, TPS650701, TPS650702, TPS650721

SLVS950G –JULY 2009–REVISED MAY 2013

www.ti.com

I2C Interface Specification:

Serial interface

The serial interface is compatible with the standard and fast mode I

C specifications, allowing transfers at up to

400kHz. The interface adds flexibility to the power supply solution, enabling most functions to be programmed to

new values depending on the instantaneous application requirements and charger status to be monitored. The

TPS6507x has a 7-Bit address: ‘1001000’, other addresses are available upon contact with the factory.

Attempting to read data from register addresses not listed in this section will result in 00h being read out. For

normal data transfer, SDAT is allowed to change only when SCLK is low. Changes when SCLK is high are

reserved for indicating the start and stop conditions. During data transfer, the data line must remain stable

whenever the clock line is high. There is one clock pulse per Bit of data. Each data transfer is initiated with a

start condition and terminated with a stop condition. When addressed, the device generates an acknowledge Bit

after the reception of each byte. The master device (microprocessor) must generate an extra clock pulse that is

associated with the acknowledge Bit. The TPS6507x device must pull down the SDAT line during the

acknowledge clock pulse so that the SDAT line is a stable low during the high period of the acknowledge clock

pulse. The SDAT line is a stable low during the high period of the acknowledge–related clock pulse. Setup and

hold times must be taken into account. During read operations, a master must signal the end of data to the slave

by not generating an acknowledge Bit on the last byte that was clocked out of the slave. In this case, the slave

TPS6507x device must leave the data line high to enable the master to generate the stop condition.

All registers are set to their default value by one of these conditions:

• Voltage is below the UVLO threshold defined with registers <UVLO1>, <UVLO0>

• PB_IN is asserted LOW for >15s (option)

Figure 39. Bit Transfer on the Serial Interface

Figure 40. START and STOP Conditions

Product Folder Links: TPS65070 TPS65072 TPS65073 TPS650731 TPS650732 TPS650701 TPS650702

TPS650721