Datasheet

TPS65070, TPS65072, TPS65073
TPS650731, TPS650732, TPS650701, TPS650702, TPS650721
SLVS950G –JULY 2009–REVISED MAY 2013 www.ti.com
RECOMMENDED OPERATING CONDITIONS (continued)
MIN NOM MAX UNIT
C
AC
Input Capacitor at AC 1 μF
C
USB
Input Capacitor at USB 1 μF
C
BAT
Capacitor at BAT pin 10 μF
C
SYS
Capacitor at SYS pin 22 100
(3)
μF
C
BYPASS
Capacitor at BYPASS pin 10 μF
C
INT_LDO
Capacitor at INT_LDO pin 2.2 μF
C
AVDD6
Capacitor at AVDD6 pin 4.7 μF
T
A
Operating ambient temperature –40 85 °C
T
J
Operating junction temperature –40 125 °C
(3) For proper soft-start
ELECTRICAL CHARACTERISTICS
VSYS = 3.6V, EN_DCDCx = VSYS, L = 2.2μH, C
OUT
= 10μF, T
A
= –40°C to 85°C typical values are at T
A
= 25°C (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
V
INDCDC
Input voltage range for DCDC converters 2.8 6.3 V
Only DCDC2, DCDC3 and LDO1 enabled, device in ON-
140
mode; DCDC converters in PFM
Per DC/DC converter, PFM mode 19 30
μA
Operating quiescent current
For LDO1 or LDO2 (either one enabled) 20 35
I
Q
Total current into VSYS, VINDCDCx, VINLDO1/2
For LDO1 and LDO2 (both enabled) 34
For wLED converter 1.5
mA
Per DC/DC converter, PWM mode 2.5
All converters, LDOs, wLED driver and ADC disabled, no
I
SD
Shutdown current input voltage at AC and USB; 8 12 μA
SYS voltage turned off
–2% 2.8 2%
Voltage at the output of the power manager detected at pin
3.0
V
UVLO
Undervoltage lockout threshold SYS; falling voltage, voltage defined with <UVLO0>, V
3.1
<UVLO1> DEFAULT: 3.0V
3.25
–2% 2.8 2%
Voltage at the output of the power manager detected at pin
3.0
Undervoltage lockout threshold for TPS650702,
V
UVLO
SYS; falling voltage, voltage defined with <UVLO0>, V
TPS650721 only
3.1
<UVLO1> DEFAULT: 2.8V
3.25
360
Rising voltage defined with <UVLO hysteresis>; DEFAULT:
Undervoltage lockout hysteresis mV
500mV
450
Undervoltage lockout deglitch time Due to internal delay 4 ms
Thermal shutdown for DCDC converters, wLED
T
SD
Increasing junction temperature 150 °C
driver and LDOs
Thermal shutdown hysteresis Decreasing junction temperature 20 °C
EN_DCDC1, EN_DCDC2, EN_DCDC3, DEFDCDC2, DEFDCDC3, SDAT, SCLK, EN_wLED (optional)
High Level Input Voltage, EN_DCDC1,
V
IH
EN_DCDC2, EN_DCDC3, DEFDCDC2, 1.2 V
SYS
V
DEFDCDC3, SDAT, SCLK, EN_wLED
Low Level Input Voltage, EN_DCDC1,
V
IL
EN_DCDC2, EN_DCDC3, DEFDCDC2, 0 0.4 V
DEFDCDC3, SDAT, SCLK, EN_wLED
Input bias current, EN_DCDC1, EN_DCDC2,
I
IN
EN_DCDC3, DEFDCDC2, DEFDCDC3, SDAT, 0.01 1.0 μA
SCLK
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Product Folder Links: TPS65070 TPS65072 TPS65073 TPS650731 TPS650732 TPS650701 TPS650702
TPS650721