Datasheet

/RESET
THRESHOLD
Vbat
delay
Vref=1V
+
-
RESET
Vbat
THRESHOLD
T
RESET
comparator
output(internal)
TPS65070, TPS65072, TPS65073
TPS650731, TPS650732, TPS650701, TPS650702, TPS650721
www.ti.com SLVS950G –JULY 2009–REVISED MAY 2013
ENABLE
To start up each converter independently, the device has a separate enable pin for each of the DCDC
converters. In order to enable any converter with its enable pins, the TPS6507x devices need to be in ON-state
by pulling PB_IN=LOW or POWER_ON=HIGH. The sequencing option programmed needs to be DCDC_SQ[2..0]
= 101.
If EN_DCDC1, EN_DCDC2, EN_DCDC3 are set to high, the corresponding converter starts up with soft start as
previously described.
Pulling the enable pin low forces the device into shutdown, with a shutdown quiescent current as defined in the
electrical characteristics. In this mode, the high side and low side MOSFETs are turned-off, and the entire
internal control circuitry is switched-off. If disabled, the outputs of the DCDC converters are pulled low by internal
250Ω resistors, actively discharging the output capacitor. For proper operation the enable pins must be
terminated and must not be left floating.
Optionally, there is internal sequencing for the DCDC converters and both LDOs available. Bits DCDC_SQ[0..2]
in register CON_CTRL1 define the start-up and shut-down sequence for the DCDC converters. Depending on
the sequencing option, the signal at EN_DCDC1, EN_DCDC2 and EN_DCDC3 are ignored. For automatic
internal sequencing, the enable signals which are not used should be connected to GND.
LDO1 and LDO2 will start up automatically as defined in register LDO_CTRL1. See details about the sequencing
options in the register description for CON_CTRL1 and LDO_CTRL1.
RESET (TPS65070, TPS650701, TPS650702, TPS650721, TPS65073, TPS650731, TPS650732 only)
The TPS6507x contain circuitry that can generate a reset pulse for a processor with a certain delay time. The
input voltage at a comparator is sensed at an input called THRESHOLD. When the voltage exceeds the
threshold, the output goes high with the delay time defined in register PGOOD. The reset circuitry is not active in
OFF-state. The pull-up resistor for this open drain output must not be connected directly to the battery as this
may cause a leakage path when the power path (SYS voltage) is turned off. The reset delay time equals the
setting for the PGOOD signal. For devices that are configured with EN_wLED input, the reset output should be
left open.
Figure 32. Reset Timing
PGOOD (reset signal for applications processor)
This open drain output generates a power-good signal depending on the status of the power good Bits for the
DCDC converters and the LDOs. Register PGOODMASK defines which of the power good Bits of the converters
and LDOs are used to drive the external PGOOD signal low when the voltage is below the target value. If e.g.,
Bit MASK DCDC2 is set to 1, the PGOOD pin will be driven low as long as the output of DCDC2 is below the
target voltage. If the output voltage of DCDC2 rises to its nominal value, the PGOOD pin will be released after
the delay time defined. See the default settings in the register description.
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Product Folder Links: TPS65070 TPS65072 TPS65073 TPS650731 TPS650732 TPS650701 TPS650702
TPS650721