Datasheet

TPS65070, TPS65072, TPS65073
TPS650731, TPS650732, TPS650701, TPS650702, TPS650721
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SLVS950G JULY 2009REVISED MAY 2013
PIN FUNCTIONS (continued)
PIN
I/O DESCRIPTION
NAME NO.
Connect a resistor from this pin to GND to set the full scale current for Isink1 and Isink2 with Bit Current
Iset2
Level in register WLED_CTRL0 set to 0.
36 I
(AD_IN7)
Analog input7 for the A/D converter.
Isink1 34 I Input to the current sink 1. Connect the cathode of the LEDs to this pin.
Isink2 33 I Input to the current sink 2. Connect the cathode of the LEDs to this pin.
Enable input for TPS6507x. When pulled LOW, the DCDC converters and LDOs start with the sequencing
PB_IN 25 I
as programmed internally. Internal 50kΩ pull-up resistor to AVDD6
Power_ON input for the internal state machine. After PB_IN was pulled LOW to turn on the TPS6507x, the
POWER_ON pin needs to be pulled HIGH by the application processor to keep the system in ON-state
POWER_ON 13 I
when PB_IN is released HIGH. If POWER_ON is released LOW, the DCDC converters and LDOs will turn
off when PB_IN is HIGH.
Open drain output. This pin is driven by the status of the /PB_IN input (after debounce). PB_OUT=LOW if
PB_OUT 24 O
PB_IN=LOW
Open drain power good output. The delay time equals the setting for Reset. The pin will go low depending
PGOOD 26 O on the setting in register PGOODMASK. Optionally it is also driven LOW for 0.5ms when PB_IN is pulled
LOW for >15s.
TPS65070, TPS65073, TPS650731, TPS650732:Input for the reset comparator. RESET will be LOW if this
THRESHOLD 47 I
voltage drops below 1V.
TPS650701, TPS650702, TPS650721, TPS65072, : This pin is the actively high enable input for the wLED
EN_wLED 47 I
driver. The wLED converter is enabled by the ENABLE ISINK Bit OR enable EN_wLED pin.
TPS65070, TPS650701, TPS650702, TPS65073, TPS650731, TPS650732:
RESET 39 O
Open drain active low reset output, reset delay time equals settings in register PGOOD. The status depends
on the voltage applied at THRESHOLD.
TPS65072:
This pin is the active high, push-pull output to enable an external LDO. This pin will be set and reset during
startup and shutdown by the sequencing option programmed. The output is pulled internally to the SYS
EN_EXTLDO 39 O
voltage if HIGH.
The output is only used for sequencing options for Sirf Prima or Atlas 4 processors with DCDC_SQ[2..0] =
100 or DCDC_SQ[2..0] = 111.
PowerPAD™ Power ground connection for the PMU. Connect to GND
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Product Folder Links: TPS65070 TPS65072 TPS65073 TPS650731 TPS650732 TPS650701 TPS650702
TPS650721