Datasheet
PIN ASSIGNMENTS
Vcc
VIN_LDO1
VLDO1
FB_LDO1
THRESH
FB_LDO2
12
11
10
9
8
7
123456
181716151413
FB_DCDC1
EN_DCDC1
EN_DCDC2
EN_LDO1
MODE
AGND
EN_LDO3
EN_LDO2
RESET
VLDO3
VINLDO2/3
VLDO2
PGND1
L1
VINDCDC1/2
L2
PGND2
FB_DCDC2
19
20
21
22
23
24
TPS65053
TPS650531
TPS650532
www.ti.com
............................................................................................................................................. SLVS754C – MARCH 2007 – REVISED SEPTEMBER 2009
RGE PACKAGE
(TOP VIEW)
PIN FUNCTIONS
PIN
I/O DESCRIPTION
NAME NO.
Power supply for digital and analog circuitry of DCDC1, DCDC2 and LDOs. This pin must be connected to the same
V
CC
1 I
voltage supply as VINDCDC1/2.
Input to adjust output voltage of converter 1 between 0.6 V and V
I
. Connect external resistor divider between VOUT1,
FB_DCDC1 19 I
this pin and GND.
Select between Power Save Mode and forced PWM Mode for DCDC1 and DCDC2. In Power Save Mode, PFM is
MODE 23 I used at light loads, PWM for higher loads. If PIN is set to high level, forced PWM Mode is selected. If Pin has low
level, then the device operates in Power Save Mode.
Input voltage for VDCDC1 and VDCDC2 step-down converter. This must be connected to the same voltage supply as
VINDCDC1/2 16 I
V
CC
.
Input to adjust output voltage of converter 2 between 0.6V and VIN. Connect external resistor divider between
FB_DCDC2 13 I
VOUT2, this pin and GND.
L1 17 O Switch pin of converter 1. Connected to Inductor
PGND1 18 I GND for converter 1
PGND2 14 I GND for converter 2
AGND 24 I Analog GND, connect to PGND and PowerPAD™
L2 15 O Switch Pin of converter 2. Connected to Inductor.
EN_DCDC1 20 I Enable Input for converter 1, active high
EN_DCDC2 21 I Enable Input for converter 2, active high
VINLDO1 2 I Input voltage for LDO1
VINLDO2/3 8 I Input voltage for LDO2 and LDO3
VLDO1 3 O Output voltage of LDO1
VLDO2 7 O Output voltage of LDO2
VLDO3 9 O Output voltage of LDO3
FB_LDO1 4 1 Feedback input for the external voltage divider.
FB_LDO2 6 I Feedback input for the external voltage divider.
EN_LDO1 22 I Enable input for LDO1. Logic high enables the LDO, logic low disables the LDO.
EN_LDO2 11 I Enable input for LDO2. Logic high enables the LDO, logic low disables the LDO.
EN_LDO3 12 I Enable input for LDO3. Logic high enables the LDO, logic low disables the LDO.
THRESHOLD 5 I Reset input
RESET 10 O Open drain active low reset output, 100 ms reset delay time.
PowerPAD™ – Connect to GND
Copyright © 2007 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): TPS65053 TPS650531 TPS650532