Datasheet

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FUNCTIONAL BLOCK DIAGRAM
L2
DEFDCDC2
EN_DCDC1
ENABLE
V
CC
VDCDC2
PGND2
EN_LDO1
ENABLE
EN_DCDC2
ENABLE
VLDO2
VLDO3
200-mA LDO
VLDO3
VLDO2
VLDO4
DCDC1(I/O)
VINDCDC1/2
L1
FB_DCDC1
PGND1
DCDC2(core)
VLDO1
400-mA LDO
VLDO1
VLDO4
200-mA LDO
VIN
VIN_LDO1
VIN_LDO3/4
ENABLE
VIN
MODE
Interface
2.2 Hm
2.2 Hm
1 Fm
1 W
10 Fm
10 Fm
10 Fm
4.7 Fm
2.2 Fm
2.2 Fm
TPS65050
ENABLE
EN_LDO2
EN_LDO3
ENABLE
EN_LDO4
DEFLDO1
DEFLDO2
DEFLDO3
DEFLDO4
0.1 Fm
BP
VIN
VIN_LDO2
Vbat
PB_OUT
AGND
PB_IN
Vbat
Flipflopwith
32-msdebounce
default
turnedon
R2
R1
R3
R4
Cff
I/Ovoltage
R19
STEP-DOWN
CONVERTER
600mA
STEP-DOWN
CONVERTER
600mA
400-mA LDO
4.7 Fm
TPS65050, TPS65051, TPS65052
TPS65054, TPS65056
SLVS710A – JANUARY 2007 – REVISED AUGUST 2007
Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Link(s): TPS65050, TPS65051, TPS65052 TPS65054, TPS65056