Datasheet

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Low Drop Out Voltage Regulators (LDOs)
R6
R5
V =
O
V x1+
ref
()
(9)
V
(FB_LDOs)
V
O
R5 =R6 x -R6
()
R6
R5+R6
V =V
O (FB_LDOs)
x
(10)
LAYOUT CONSIDERATIONS
Application Circuits
PB-ONOFF and Sequencing
TPS65050, TPS65051, TPS65052
TPS65054, TPS65056
SLVS710A – JANUARY 2007 – REVISED AUGUST 2007
The output voltage of all 4 LDOs in TPS65051, TPS65054 and TPS65056 are set by an external resistor
network. The output voltage is calculated using Equation 9 :
with an internal reference voltage, V
ref
, 1 V (typical)
Setting the total resistance of R5 + R6 to less than 1 M Ω is recommended. Typically, there is no feedforward
capacitor needed at the voltage dividers for the LDOs.
Typical resistor values:
Table 6. Typical Resistor Values
OUTPUT VOLTAGE R5 R6 NOMINAL VOLTAGE
3.3 V 300 k Ω 130 k Ω 3.31 V
3 V 300 k Ω 150 k Ω 3 V
2.85 V 240 k Ω 130 k Ω 2.85 V
2.8 V 360 k Ω 200 k Ω 2.8 V
2.5 V 300 k Ω 200 k Ω 2.5 V
1.8 V 240 k Ω 300 k Ω 1.8 v
1.5 V 150 k Ω 300 k Ω 1.5 V
1.3 V 36 k Ω 120 k Ω 1.3 V
1.2 V 100 k Ω 510 k Ω 1.19 V
1.1 V 33 k Ω 330 k Ω 1.1 V
The PB-ONOFF output can be used to enable one or several converters. After power up, the PB_OUT pin is low,
and pulls down the enable pins connected to PB_OUT; EN_DCDC1, and EN_LDO1 in Figure 24 . When PB_IN is
pulled to V
CC
for longer than 32 ms, the PB_OUT pin is turned off, hence the enable pins pulled high using a
pull-up resistor to V
CC
. This enables the DCDC1 converter and LDO1. The output voltage of DCDC1 (V
OUT
1) is
used as the enable signal for DCDC2 and LDO2 to LDO4. LDO1 with its output voltage of 3.3 V and LDO2 for an
output voltage of 2.5 V are powered from the battery (V
(bat)
) directly. To save power, the input voltage for the
lower voltage rails at LDO3 and LDO4 are derived from the output of the step-down converters, keeping the
voltage drop at the LDOs low to increase efficiency. As LDO3 and LDO4 are powered from the output of DCDC1,
the total output current on V
OUT
1, LDO3 and LDO4 must not exceed the maximum rating of DCDC1.
Figure 25 shows the power up timing for this application.
28 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): TPS65050, TPS65051, TPS65052 TPS65054, TPS65056