Datasheet

UNDERVOLTAGE LOCKOUT
POWER-UP SEQUENCING
PWRFAIL
DESIGN PROCEDURE
Inductor Selection for the dcdc Converters
DI
L
+ Vout
1 *
Vout
Vin
L ƒ
I
Lmax
+ I
outmax
)
DI
L
2
(4)
TPS650250
SLVS843 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com
The undervoltage lockout circuit for the five regulators on the TPS650250x prevents the device from
malfunctioning at low input voltages and from excessive discharge of the battery. It disables the converters and
LDOs. The UVLO circuit monitors the Vcc pin; the threshold is set internally to 2.35V with 5% (120mV)
hysteresis. Note that when any of the DC/DC converters are running there is an input current at the Vcc pin,
which can be up to 3mA when all three converters are running in PWM mode. This current needs to be taken
into consideration if an external RC filter is used at the Vcc pin to remove switching noise from the TPS650250x
internal analog circuitry supply. See the Vcc-Filter section for details on the external RC filter.
The TPS650250x power-up sequencing is designed to be entirely flexible and customer driven; this is achieved
simply by providing separate enable pins for each switch-mode converter and a common enable signal for LDO1
and LDO2. The relevant control pins are described in Table 1 .
Table 1. Control Pins for DCDC Converters
INPUT/
PIN NAME FUNCTION
OUTPUT
DEFDCDC3 I Defines the default voltage of the VDCDC3 switching converter set with an eternal resistor divider.
DEFDCDC2 I Defines the default voltage of the VDCDC2 switching converter. DEFDCDC2 = 0 defaults VDCDC2 to 1.8V,
DEFDCDC2 = VCC defaults VDCDC2 to 2.5V.
DEFDCDC1 I Defines the default voltage of the VDCDC1 switching converter. DEFDCDC1 = 0 defaults VDCDC1 to 2.80V,
DEFDCDC1 = VCC defaults VDCDC1 to 3.3V.
EN_DCDC3 I Set EN_DCDC3 = 0 to disable or EN_DCDC3 = 1 to enable the VDCDC3 converter
EN_DCDC2 I Set EN_DCDC2 = 0 to disable or EN_DCDC2 = 1 to enable the VDCDC2 converter
EN_DCDC1 I Set EN_DCDC1 = 0 to disable or EN_DCDC1 = 1 to enable the VDCDC1 converter
The PWRFAIL signal is generated by a voltage detector at the PWRFAIL_SNS input. The input signal is
compared to a 1V threshold (falling edge) with 5% (50mV) hysteresis. PWRFAIL is an open drain output which is
actively low when the input voltage at PWRFAIL_SNS is below the threshold.
The three converters operate with 2.2uH output inductors. Larger or smaller inductor values can be used to
optimize performance of the device for specific conditions. The selected inductor has to be rated for its dc
resistance and saturation current. The dc resistance of the inductor influences directly the efficiency of the
converter. Therefore, an inductor with the lowest dc resistance should be selected for the highest efficiency.
For a fast transient response, a 2.2 µ H inductor in combination with a 22 µ F output capacitor is recommended. For
an output voltage above 2.8V, an inductor value of 3.3 µ H minimum is required. Lower values result in an
increased output voltage ripple in PFM mode. The minimum inductor value is 1.5 µ H, but an output capacitor of
22 µ F minimum is needed in this case.
Equation 4 calculates the maximum inductor current under static load conditions. The saturation current of the
inductor should be rated higher than the maximum inductor current as calculated with Equation 4 . This is
recommended because during heavy load transient the inductor current rises above the calculated value.
With:
f = Switching frequency (2.25 MHz typical)
L = Inductor value
Δ I
L
= Peak-to-peak inductor ripple current
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