Datasheet

I
PFMDCDC1leave
+
VINDCDC 1
18 W
I
PFMDCDC2leave
+
VINDCDC 2
20 W
I
PFMDCDC3enter
+
VINDCDC 3
29 W
(2)
SOFT START
100% DUTY CYCLE LOW DROPOUT OPERATION
Vin
min
+ Vout
min
) Iout
max
ǒ
RDSon
max
) R
L
Ǔ
(3)
LOW DROPOUT VOLTAGE REGULATORS
TPS650250
www.ti.com ........................................................................................................................................................................................... SLVS843 – DECEMBER 2008
If the load is below the delivered current then the output voltage rises until the same threshold is crossed in the
other direction. All switching activity ceases, reducing the quiescent current to a minimum until the output voltage
has again dropped below the threshold. The power save mode is exited, and the converter returns to PWM mode
if either of the following conditions are met:
1. The output voltage drops 2% below the nominal V
O
due to increased load current
2. The PFM burst time exceeds 16 × 1/fs (7.1 µ s typical)
These control methods reduce the quiescent current to typically 14 µ A per converter and the switching activity to
a minimum thus achieving the highest converter efficiency. Setting the comparator thresholds at the nominal
output voltage at light load current results in a very low output voltage ripple. The ripple depends on the
comparator delay and the size of the output capacitor; increasing capacitor values makes the output ripple tend
to zero. Power Save Mode can be disabled by pulling the MODE pin high. This forces all DC/DC converters into
fixed frequency PWM mode.
Each of the three converters has an internal soft start circuit that limits the inrush current during start-up. The soft
start is realized by using a very low current to initially charge the internal compensation capacitor. The soft start
time is typically 750 µ s if the output voltage ramps from 5% to 95% of the final target value. If the output is
already pre-charged to some voltage when the converter is enabled, then this time is reduced proportionally.
There is a short delay of typically 170 µ s between the converter being enabled and switching activity actually
starting. This is to allow the converter to bias itself properly, to recognize if the output is pre-charged, and if so, to
prevent discharging of the output while the internal soft start ramp catches up with the output voltage.
The TPS650250x converters offer a low input to output voltage difference while still maintaining operation with
the use of the 100% duty cycle mode. In this mode the P-channel switch is constantly turned on. This is
particularly useful in battery-powered applications to achieve the longest operation time by taking full advantage
of the whole battery voltage range. The minimum input voltage required to maintain DC regulation depends on
the load current and output voltage and can be calculated as:
With:
Iout
max
= Maximum load current (note: ripple current in the inductor is zero under these conditions)
RDSon
max
= Maximum P-channel switch RDSon
R
L
= DC resistance of the inductor
Vout
min
= Nominal output voltage minus 2% tolerance limit
The low dropout voltage regulators are designed to operate well with low value ceramic input and output
capacitors. They operate with input voltages down to 1.5V. The LDOs offer a maximum dropout voltage of
300mV at the rated output current. Each LDO sports a current limit feature. Both LDOs are enabled by the
EN_LDO pin. The LDOs also have reverse conduction prevention. This allows the possibility to connect external
regulators in parallel in systems with a backup battery. The TPS650250 step-down and LDO voltage regulators
automatically power down when the Vcc voltage drops below the UVLO threshold or when the junction
temperature rises above 160 ° C.
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