Datasheet

V
OUT
+ V
FBLDOx
R5 ) R6
R6
R5 + R6
ǒ
V
OUT
V
FBLDOx
Ǔ
* R6
TPS650250-Q1
SLVSAA7 –MARCH 2010 www.ti.com
Vdd_alive Output
The Vdd_alive LDO is typically connected to the Vdd_alive input of the Samsung application processor. It
provides an output voltage of 1V at 30mA. It is recommended to add a capacitor of 2.2mF minimum to the
Vdd_alive pin. The LDO can be disabled by pulling the EN_Vdd_alive pin to GND.
LDO1 and LDO2
The LDOs in the TPS650250 are general purpose LDOs which are stable using ceramics capacitors. The
minimum output capacitor required is 2.2mF. The LDOs output voltage can be changed to different voltages
between 1V and 3.3V using an external resistor divider. Therefore they can also be used as general purpose
LDOs in the application. The supply voltage for the LDOs needs to be connected to the VINLDO pin, giving the
flexibility to connect the lowest voltage available in the system and therefore providing the highest efficiency.
The total resistance (R5+R6) of the voltage divider should be kept in the 1MΩ range in order to maintain high
efficiency at light load. V
FBLDOx
= 1.0V.
Vcc-Filter
An RC filter connected at the Vcc input is used to keep noise from the internal supply for the bandgap and other
analog circuitry. A typical value of 1Ω and 1mF is used to filter the switching spikes, generated by the DC/DC
converters. A larger resistor than 10Ω should not be used because the current into Vcc of up to 2.5mA causes a
voltage drop at the resistor causing the undervoltage lockout circuitry connected at Vcc internally to switch off too
early.
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Product Folder Link(s): TPS650250-Q1