Datasheet
Table Of Contents
- 1 Introduction
- 2 TPS650250EVM Electrical Performance Specifications
- 3 Modifications
- 4 Schematic
- 5 Connector and Test Point Descriptions
- 5.1 J1 –VIN
- 5.2 J2 – GND
- 5.3 J3 – VINLDO/GND
- 5.4 J4 – VDCDC1
- 5.5 J5 – GND
- 5.6 J6 – VDCDC2
- 5.7 J7 – GND
- 5.8 J8 – VDCDC3
- 5.9 J9 – GND
- 5.10 J10 – VDLO1
- 5.11 J11 – GND
- 5.12 J12 – VDLO2
- 5.13 J13 – GND
- 5.14 J14 – VDD_ALIVE/GND
- 5.15 J15 – PWRFAIL/GND
- 5.16 JP1 – EN_DCDC1
- 5.17 JP2 – EN_DCDC2
- 5.18 JP3 – EN_DCDC3
- 5.19 JP4 – EN_LDO
- 5.20 JP5 – SCALE_DCDC3
- 5.21 JP6 – MODE
- 5.22 JP7 – EN_VDD_ALIVE
- 5.23 JP8 – DEF1
- 5.24 JP9 – DEF2
- 5.25 Factory Jumper Setup
- 6 EVM Assembly Drawings and Layout
6 EVM Assembly Drawings and Layout
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EVM Assembly Drawings and Layout
Table 2. TPS650250 EVM Factory Jumper Setup (continued)
Jumper Shunt Location
JP7 Between ON and VDD_ALIVE VDD_ALIVE enabled
JP8 Between V-HI and DEF1 DCDC1 set to 3.3 V
JP6 Between PWM and MODE
JP9 Between V-LOW and DEF2 DCDC2 set to 1.8 V
Figure 3 through Figure 8 show the design of the TPS650250EVM printed circuit board. The EVM has
been designed using a 4-Layer, 1oz copper-clad circuit board 2.2” × 3.3”
Figure 3. TPS650250 EVM Top Assembly
SLVU290 – July 2009 Using the TPS650250EVM Power Management IC for Li-Ion Powered Systems 9
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