Datasheet
Table Of Contents
- 1 Introduction
- 2 TPS650250EVM Electrical Performance Specifications
- 3 Modifications
- 4 Schematic
- 5 Connector and Test Point Descriptions
- 5.1 J1 –VIN
- 5.2 J2 – GND
- 5.3 J3 – VINLDO/GND
- 5.4 J4 – VDCDC1
- 5.5 J5 – GND
- 5.6 J6 – VDCDC2
- 5.7 J7 – GND
- 5.8 J8 – VDCDC3
- 5.9 J9 – GND
- 5.10 J10 – VDLO1
- 5.11 J11 – GND
- 5.12 J12 – VDLO2
- 5.13 J13 – GND
- 5.14 J14 – VDD_ALIVE/GND
- 5.15 J15 – PWRFAIL/GND
- 5.16 JP1 – EN_DCDC1
- 5.17 JP2 – EN_DCDC2
- 5.18 JP3 – EN_DCDC3
- 5.19 JP4 – EN_LDO
- 5.20 JP5 – SCALE_DCDC3
- 5.21 JP6 – MODE
- 5.22 JP7 – EN_VDD_ALIVE
- 5.23 JP8 – DEF1
- 5.24 JP9 – DEF2
- 5.25 Factory Jumper Setup
- 6 EVM Assembly Drawings and Layout
5.9 J9 – GND
5.10 J10 – VDLO1
5.11 J11 – GND
5.12 J12 – VDLO2
5.13 J13 – GND
5.14 J14 – VDD_ALIVE/GND
5.15 J15 – PWRFAIL/GND
5.16 JP1 – EN_DCDC1
5.17 JP2 – EN_DCDC2
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Connector and Test Point Descriptions
J9 is the return connection of VDCDC2 output rail. A load can be connected between J9 and J8
(VDCDC3).
This header is the positive output of LDO1 linear regulator. This output is externally adjustable for the
TPS650250 and is programmed to a value of 2.5-V on the EVM. The VLDO1 output is capable of
supplying up to 200-mA. A load can be connected between J10 and J11 (GND).
J11 is the return connection of VLDO1 output rail. A load can be connected between J11 and J10
(VLDO1).
This header is the positive output of LDO2 linear regulator. This output is externally adjustable for the
TPS650250 and is programmed to a value of 1.4-V on the EVM. The VLDO2 output is capable of
supplying up to 200-mA. A load can be connected between J12 and J13 (GND).
J11 is the return connection of VLDO2 output rail. A load can be connected between J13 and J12
(VLDO2).
This header is the positive output of LDO3 VDD_ALIVE. The output voltage is fixed to 1.0V in the
TPS650250.
The VDD_ALIVE output is capable of sourcing up to 30mA of load current. A load can be connected
between J14 pin1 (VDD_ALIVE) and pin2 (GND).
In applications that use Samsung application processors the VDD_ALIVE output is typically connected to
the VDD_ALIVE input of the application processor.
PWRFAIL is an open drain output, that is pulled up to VIN. PWRFAIL goes low if the PWRFAIL_SNS input
falls below 1.0V. On the EVM the default settings is PWRFAIL goes low when VIN falls below 3.4V. This
threshold can be changed by modifying the resistor network R5 and R6.
Placing a shorting bar between EN_DCDC1 and ON ties the EN pin of DCDC1 to VIN, thereby enabling
DCDC1. Placing a shorting bar between EN_DCDC1 and OFF ties the EN pin of DCDC1 to GND, thereby
disabling DCDC1.
Placing a shorting bar between EN_DCDC2 and ON ties the EN pin of DCDC2 to VIN, thereby enabling
DCDC2. Placing a shorting bar between EN_DCDC2 and OFF ties the EN pin of DCDC2 to GND, thereby
disabling DCDC2.
SLVU290 – July 2009 Using the TPS650250EVM Power Management IC for Li-Ion Powered Systems 7
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