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User's Guide

SLVU290 – July 2009

Using the TPS650250EVM Power Management IC for Li-Ion

Powered Systems

The TPS650250EVM is an integrated Power Management evaluation tool for use of the TPS650250 in

applications that are powered with one Li-Ion or Li-Polymer cell and require multiple power rails. The

TPS650250 contains three adjustable highly efficient switching step-down converters, three LDOs, and

additional status and I/O pins.

Contents

1 Introduction ................................................................................................................... 2

2 TPS650250EVM Electrical Performance Specifications ................................................................ 3

3 Modifications.................................................................................................................. 4

4 Schematic ..................................................................................................................... 5

5 Connector and Test Point Descriptions ................................................................................... 6

6 EVM Assembly Drawings and Layout ..................................................................................... 9

List of Figures

1 Voltage Scaling Circuit ...................................................................................................... 4

2 TPS650250 EVM Schematic ............................................................................................... 5

3 TPS650250 EVM Top Assembly .......................................................................................... 9

4 TPS650250EVM Top and Silkscreen (Viewed from Top) ............................................................. 10

5 TPS650250EVM Top Copper ............................................................................................ 10

6 TPS650250 EVM Layer 2 (GND Plane) ................................................................................. 11

7 TPS650250EVM Internal Layer 3 ....................................................................................... 11

8 TPS650250 EVM Bottom Layer .......................................................................................... 12

List of Tables

1 TPS650250EVM Electrical and Performance Specifications .......................................................... 3

2 TPS650250 EVM Factory Jumper Setup ................................................................................. 8

3 TPS650250EVM Bill of Materials ........................................................................................ 13

SLVU290 – July 2009 Using the TPS650250EVM Power Management IC for Li-Ion Powered Systems 1

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Summary of content (14 pages)

PAGE 1
User's Guide SLVU290 – July 2009 Using the TPS650250EVM Power Management IC for Li-Ion Powered Systems The TPS650250EVM is an integrated Power Management evaluation tool for use of the TPS650250 in applications that are powered with one Li-Ion or Li-Polymer cell and require multiple power rails. The TPS650250 contains three adjustable highly efficient switching step-down converters, three LDOs, and additional status and I/O pins. 1 2 3 4 5 6 Contents Introduction .........................................
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Introduction 1 Introduction 1.1 Description www.ti.com The TPS650250 provides three highly efficient, step-down converters targeted at providing the core voltage, peripheral, I/O and memory rails in a processor based system. All three step-down converters enter a low power mode at light load for maximum efficiency across the widest possible range of load currents. The converters can be forced into fixed frequency PWM mode by pulling the MODE pin high.
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TPS650250EVM Electrical Performance Specifications www.ti.com 2 TPS650250EVM Electrical Performance Specifications Table 1. TPS650250EVM Electrical and Performance Specifications Parameter Notes & Conditions Min Nom Max Units 3.3 5.5 INPUT CHARACTERISTICS VIN Input Voltage VIN_UVLO Input UVLO VIN falling 2.35 V V OUTPUT CHARACTERISTICS VOUT_DCDC1 VOUT_DCDC2 VOUT_DCDC3 Output Voltage DCDC1 Output Voltage DCDC2 VIN = Nom, IOUT = Nom Vin = 3.
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Modifications www.ti.com 3 Modifications 3.1 Voltage Scaling for DCDC3 The output voltage of DCDC3 is externally adjustable with the resistor divider network R10 and R11. The factory EVM configuration is R10 = 182k and R11 = 182k, resulting in an output voltage of 1.2V. See the TPS650250 data sheet (SLVS843) for assistance on changing the output voltage. DCDC3 has no preset default output voltages as DCDC1 and DCDC2.
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Schematic www.ti.com 4 Schematic Figure 2.
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Connector and Test Point Descriptions 5 Connector and Test Point Descriptions 5.1 J1 –VIN www.ti.com This header is the positive connection to the input power supply. The power supply must be connected between J1 and J2 (GND). The leads to the input supply should be twisted and kept as short as possible. The input voltage has to be between 3.3-V and 6-V. 5.2 J2 – GND This header is the return connection to the input power supply. Connect the power supply between J12 and J1 (VIN).
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www.ti.com 5.9 Connector and Test Point Descriptions J9 – GND J9 is the return connection of VDCDC2 output rail. A load can be connected between J9 and J8 (VDCDC3). 5.10 J10 – VDLO1 This header is the positive output of LDO1 linear regulator. This output is externally adjustable for the TPS650250 and is programmed to a value of 2.5-V on the EVM. The VLDO1 output is capable of supplying up to 200-mA. A load can be connected between J10 and J11 (GND). 5.
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Connector and Test Point Descriptions www.ti.com 5.18 JP3 – EN_DCDC3 Placing a shorting bar between EN_DCDC3 and ON ties the EN pin of DCDC3 to VIN, thereby enabling DCDC3. Placing a shorting bar between EN_DCDC3 and OFF ties the EN pin of DCDC3 to GND, thereby disabling DCDC1. 5.19 JP4 – EN_LDO Placing a shorting bar between EN_ LDO and ON ties the pin EN_LDO to VIN, thereby enabling LDO1 and LDO2. Placing a shorting bar between EN_LDO and OFF ties the pin EN_LDO to GND, thereby disabling LDO1 and LDO2.
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EVM Assembly Drawings and Layout www.ti.com Table 2. TPS650250 EVM Factory Jumper Setup (continued) Jumper 6 Shunt Location JP7 Between ON and VDD_ALIVE VDD_ALIVE enabled JP8 Between V-HI and DEF1 DCDC1 set to 3.3 V JP6 Between PWM and MODE JP9 Between V-LOW and DEF2 DCDC2 set to 1.8 V EVM Assembly Drawings and Layout Figure 3 through Figure 8 show the design of the TPS650250EVM printed circuit board. The EVM has been designed using a 4-Layer, 1oz copper-clad circuit board 2.2” × 3.
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EVM Assembly Drawings and Layout www.ti.com TEXAS INSTRUMENTS Figure 4. TPS650250EVM Top and Silkscreen (Viewed from Top) Figure 5.
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EVM Assembly Drawings and Layout www.ti.com Figure 6. TPS650250 EVM Layer 2 (GND Plane) Figure 7.
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EVM Assembly Drawings and Layout www.ti.com Figure 8.
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EVM Assembly Drawings and Layout www.ti.com 6.1 Bill of Materials Table 3 lists the EVM components as configured according to the schematic shown in Figure 2. Table 3. TPS650250EVM Bill of Materials Count RefDes Value Description Size Part Number MFR 2 C1, C5 1.0µF Capacitor, Ceramic, 6.3V, X5R,10% 0603 C1608X5R0J105K TDK 4 C12, C13, C14, C15 2.2µF Capacitor, Ceramic, 6.3V, X5R, 10% 0603 C1608X5R0J225K TDK 9 C2, C3, C4, C6, 10uF C7, C8, C9, C10, C11 Capacitor, Ceramic, 6.
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