Datasheet

VDCDC3
DCDC3_EN
DEFDCDC3
AGND PGND
L3
R1
R2
V
O
L
C
O
V
CC
VINDCDC3
C
I
1 Fm
10R
V
(bat)
V
OUT DEFDCDCx
=V x
R1+R2
R2
R1=R2x
V
OUT
V
DEFDCDCx
-R2
()
TPS65023, TPS65023B
SLVS670J –JUNE 2006– REVISED SEPTEMBER 2011 www.ti.com
Table 6. Possible Capacitors
CAPACITOR VALUE CASE SIZE COMPONENT SUPPLIER COMMENTS
22 μF 1206 TDK C3216X5R0J226M Ceramic
22 μF 1206 Taiyo Yuden JMK316BJ226ML Ceramic
22 μF 0805 TDK C2012X5R0J226MT Ceramic
22μF 0805 Taiyo Yuden JMK212BJ226MG Ceramic
10 μF 0805 Taiyo Yuden JMK212BJ106M Ceramic
10 μF 0805 TDK C2012X5R0J106M Ceramic
Output Voltage Selection
The DEFDCDC1, DEFDCDC2, and DEFDCDC3 pins are used to set the output voltage for each step-down
converter. See Table 7 for the default voltages if the pins are pulled to GND or to VCC. If a different voltage is
needed, an external resistor divider can be added to the DEFDCDCx pin as shown in Figure 36.
The output voltage of VDCDC1 is set with the I
2
C interface. If the voltage is changed from the default, using the
DEFCORE register, the output voltage only depends on the register value. Any resistor divider at DEFDCDC1
does not change the voltage set with the register.
Table 7.
PIN LEVEL DEFAULT OUTPUT VOLTAGE
VCC 1.6 V
DEFDCDC1
GND 1.2 V
VCC 3.3 V
DEFDCDC2
GND 1.8 V
VCC 3.3 V
DEFDCDC3
GND 1.8 V
Using an external resistor divider at DEFDCDCx:
Figure 36. External Resistor Divider
When a resistor divider is connected to DEFDCDCx, the output voltage can be set from 0.6 V up to the input
voltage V
(bat)
. The total resistance (R1+R2) of the voltage divider should be kept in the 1-MR range in order to
maintain a high efficiency at light load.
V
(DEFDCDCx)
= 0.6 V
(8)
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