Datasheet

TPS65023, TPS65023B

www.ti.com

SLVS670J –JUNE 2006– REVISED SEPTEMBER 2011

CON_CTRL2. Register Address: 05h (read/write) Default Value: 40h

CON_CTRL2 B7 B6 B5 B4 B3 B2 B1 B0

Bit name and Core adj DCDC2 DCDC1 DCDC3

function allowed discharge discharge discharge

Default 0 1 0 0 0 0 0 0

Default value UVLO + RESET(1)

UVLO UVLO UVLO

loaded by: DONE

Read/Write R/W R/W R/W R/W R/W

The CON_CTRL2 register can be used to take control the inductive converters.

RESET(1): CON_CTRL2[6] is reset to its default value by one of these events:

• undervoltage lockout (UVLO)

• HOT_RESET pulled low

• RESPWRON active

• VRTC below threshold

Bit 7 GO:

0 = no change in the output voltage for the DCDC1 converter

1 = the output voltage of the DCDC1 converter is changed to the value defined in DEFCORE with

the slew rate defined in DEFSLEW. This bit is automatically cleared when the DVM transition is

complete. The transition is considered complete in this case when the desired output voltage

code has been reached, not when the VDCDC1 output voltage is actually in regulation at the

desired voltage.

Bit 6 CORE ADJ Allowed:

0 = the output voltage is set with the I

C register

1 = DEFDCDC1 is either connected to GND or VCC or an external voltage divider. When

connected to GND or VCC, VDCDC1 defaults to 1.2 V or 1.6 V respectively at start-up

Bit 2– 0 0 = the output capacitor of the associated converter is not actively discharged when the converter is

disabled

1 = the output capacitor of the associated converter is actively discharged when the converter is

disabled. This decreases the fall time of the output voltage at light load

Product Folder Link(s) :TPS65023 TPS65023B